From: Ronald E. Nikel ([email protected])
Date: Tue Oct 17 2000 - 07:41:23 PDT
RE: [SI-LIST] : 2.5 Gbps across a backplaneWell that is only partially true.
Equalization can be done anywhere using silicon, discrete filters or the
interconnect itself.
Equalization can be done :
1) on silicon using discrete filter components
2) on silicon using active devices
3) on the PCB using discrete or active components - see HIPPI-6400
4) in the interconnect using proprietary interconnect - See Gore Cable
Interconnect
My personal favorite approach is to use active equalization in silicon and
working with interconnect folks to reduce loss of interconnect to a known
band of loss for length ranges, the rest is done in firmware.
Ron.
-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of Larry Miller
Sent: Tuesday, October 17, 2000 6:44 AM
To: [email protected]
Subject: RE: [SI-LIST] : 2.5 Gbps across a backplane
It is done inside ASICs. At the frequencies of interest discrete parts
would be problematic; digital FIR filter techniques are needed for
picosecond pole and zero time constants.
Broadcom makes one of the most widely available adaptively-equalized
serial backplane drivers for general use. I'm sure there are others.
This is getting to be a Big Deal with increasing speeds in networking
gear.
In the context of Fibre Channel and 10 Gigabit Ethernet transceivers the
equalizers are done in the interface ICs. Some of these may actually be
mounted inside the optical transceivers.
Larry Miller
-----Original Message-----
From: DORIN OPREA [SMTP:[email protected]]
Sent: Tuesday, October 17, 2000 5:52 AM
To: [email protected]
Subject: Re: [SI-LIST] : 2.5 Gbps across a backplane
Hi,
Can somebody describe in detail the way the equalization is done ?
Are the equalizors ICs or filters ? What is the name of the device ?
Thanks,
Dorin
"Dr. Edward P. Sayre" wrote:
> Folks:
>
> A subtle issue came up in the recent T11 (Fibre Channel) meetings.
How do
> you spec an interconnect when adaptive equalization parts will be used
to
> dig out the signal? If you have really good eye-diagrams response
then do
> you need equalization? Conversely, if you need equalization because of
> excessive deterministic jitter (read that insufficient rise time
bandwidth)
> or eye closure (read that too much attenuation) or both, then what
> constitutes an acceptable way to specify the interconnect, be it
backplane,
> cable or connector?
>
> Now, the question of cross talk corruption of the signals is another
> matter, especially when equalization is involved. Cross talk can be of
no
> consequence or it can be of terrible consequence, especially if there
is a
> requirement for byte (a 4 bit nibble) aligned serial data streams.
Our
> work indicates that connector cross talk in differential connectors
appears
> to be essentially dV/dt noise due to any asymmetries in the geometry
of the
> connector or interconnect (vias count here!). Although small, and
> generally in the (1 - 4%) range, it is obviously a problem when many
lines
> are switching and especially if the time alignment is not within a
small %
> of the rise time between individual differential components. If the
signal
> is broken into its even (common mode) and odd (differential) mode
> components, it can be shown that very soon the common mode cross talk
> dominates the cross talk.
>
> So, when is cross talk an equalization issue from a differential eye
> diagram point of view; and can equalization help from an EMI point of
view?
> I look forward to folks' ideas on this matter.
>
> ed sayre
>
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> | NORTH EAST SYSTEMS ASSOCIATES, INC. |
> | ------------------------------------- |
> | "High Performance Engineering & Design" |
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
> | Dr. Ed Sayre e-mail: [email protected] |
> | NESA, Inc. http://www.nesa.com/ |
> | 636 Great Road Tel +1.978.897-8787 |
> | Stow, MA 01775 USA Fax +1.978.897-5359 |
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+
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