Re: [SI-LIST] : 2.5Gbps across a backplane?

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From: Mike Jenkins (jenkins@lsil.com)
Date: Fri Oct 13 2000 - 19:30:09 PDT


Ladies & gentlemen,

My apologies for taking so long to respond to those who asked for
the pre-emphasis presentation. There were quite a few requests,
so I have resorted to putting the PDF on this anonymous ftp site:
        ftp://ftp0.lsil.com/pub/CMOSat3125.pdf
Netscape should provide you the file directly. Alternately:
        ftp ftp0.lsil.com
        Name: anonymous
        Password: <email id>
        cd pubs
        get CMOSat3125.pdf
The file will be removed fairly soon, so those who still want it,
please don't wait too long. I'll check Monday and reload it,
if needed. The PCB cross section is also included below.
Thanks to all who expressed interest.

Let me also reply to some interesting comments on pre-emphasis
by Jinhua Chen (quoted below). Jinhua makes the point that
pre-emphasis can be optimized for only one assumed line
attenuation, that is, only one length. This is theoretically true.
Still, two considerations are transforming pre-emphasis from the
lab curiosity that it was into a valuable (and possibly necessary)
technique at multi-gigabit speeds:

1) Interoperable standards (Fibre Channel, for example) required
serdes from different manufacturers to communicate across lengths
from a few inches to tens of meters. At 3+Gb/s (the coming
10Gb Ethernet and Fibre Channel standards), lengths are limited
to about 20 inches of PCB. Also, generally a single system
integrator controls that path length AND controls the firmware
that would set the pre-emphasis amount.

2) While a fixed pre-emphasis setting may not be "optimal" over
a range of lengths, it can be good enough. I suspect (but haven't
tried to prove rigorously) that finite risetimes can allow fixed
pre-emphasis to be effective across a wider range of lengths due to
the lack of high frequency components. While the PDF on the ftp
site shows only data eyes after 20 inches of PCB, the same settings
were optimal for 5 inches of PCB (and those data eyes looked even
cleaner, of course). Maybe not optimal, but adequately sub-optimal.

Regards,
Mike Jenkins

  ----------------------------------------------------------------

        Here's the cross section. There's more info in the PDF.

 |<-- 0.015" -->|<----------- 0.035" ------------>|<-- 0.015" -->|
  ______________ ______________
 |______________| <------ 0.74 ounce Cu --------> |______________|
         |
         |
       0.008" FR-4
         |
_________|__________________________________________________________
////////////////////////////////////////////////////////////////////

        The signal traces are on an outside plane (i.e., microstrip).

Jinhua Chen wrote:
>
> Hi, Mike
>
> Could you send a copy of pre-emphasis at 3.125G across 20 inches
> of FR4 (microstrip) to me? I am very interested in the pre-emphasis
> data. In general, the loss is linear to the length of PCB. The pre-emphasis
> is trying to compensate for the high frequency PCB loss (dielectric loss +
> skin effect loss). Assume the pre-emphasis is designed to compensate for L
> inches
> of FR4 material. When the real PCB length is shorter than L, the pre-emphasis
> may over compensate. When the real PCB length is longer than L, the
> pre-emphasis
> may under compensate. Different dielectric material might have different
> L. It is hard to optimize the signals with pre-emphasis.
>
> This is just my 2 cents!
>
> Regards!
  ...

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 Mike Jenkins               Phone: 408.433.7901            _____     
 LSI Logic Corp, ms/G715      Fax: 408.433.7461        LSI|LOGIC| (R)   
 1525 McCarthy Blvd.       mailto:Jenkins@LSIL.com        |     |     
 Milpitas, CA  95035         http://www.lsilogic.com      |_____|    
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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