From: Bill Cohen ([email protected])
Date: Fri Oct 13 2000 - 11:15:11 PDT
Lynne Greeen wrote:
> Where I used to work, we received a dual-voltage I/O cell
> design from a contractor that worked ONLY if the power
> supplies tracked. And other I/O cells could fall out of spec
> at any Vcc1/Vcc2/Temp/Process corner, depending on the
> circuit design.
This is becoming a problem that will have to be delt with more and more. To
get the speed and power products the core logic voltages are not the same as
the IO voltages. Now more than one type of IO voltage is required.
Sometimes up to three (HSTL (1.5V), SSTL(2.5V), LVTTL (3.3V)) voltages
are required just for the IO especially in the ASIC arena.
Most times cells fall out of compliance due to SSO (simultaneous
switching outputs) that leads to power supply noise. This may
lead to propagation delay that is greater than expected due to
circuit interactions between power supplies and circuits.
One way of reducing these effects are better packages with reduced
power supply inductances (i.e. reducing ground bounce). Another way
is to design circuits that are less sensitive to power supply fluctuations.
To reduce IO bounce some slew rate limiting circuits have been tried.
While limiting the slew rate and reducing ground bounce some have actually
increased power supply sensitivity. In some cases going back to a generic
buffer increased the power supply bounce but solved the power supply
sensitivity problem.
Bill Cohen
Toshiba America
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