From: Sunil Kumar (firstname.lastname@example.org)
Date: Thu Oct 12 2000 - 09:05:00 PDT
Yes, DC fans are being used. I have already tried that. I had powered up
fans from separate power supply. But still I did see increase in jitter.
On Thu, 12 Oct 2000, Patrick Lawler wrote:
> If a DC fan is being used, the pulsating current load current may be
> feeding back through the power supply into the logic circuitry.
> This applies whether the fan is brush or brushless.
> If this is your situation, try powering the fan from a separate power
> supply to see if the symptom goes away.
> On Thu, 12 Oct 2000 11:41:55 +0500 (GMT+0500), Sunil Kumar
> <email@example.com> wrote:
> >I am measuring cycle-to-cycle jitter in clock in a system, where clock
> >(PECL, 50MHz) is going from one PCB (card) to other through twinax
> >cable. In the second card clock is converted into TTL and then distributed
> >to various ICs. I am looking at the clock just before the PECL-to-TTL
> >convertor. Both the cards are in the same backplane. The system is
> >equiped with a set of fans for cooling, which are kept below the card
> >frame. Now what I have observed is, when the fans are not on, jitter is
> >much much less in comparision of the jitter when fans are on. I think, the
> >fans are generating EMI, which is disturbing the planes in the backplane
> >and the cards, and hence jitter is increased. Any explanations?
> >One more thing which I have observed is, the PECL-to-PECL clock
> >fanout buffer (no PLL inside) is reducing jiiter (with fans off), i.e.
> >jitter at input is more than that at output. Can anybody explain this?
> >Is there any PECL-to-TTL clock fanout buffer which adds very low
> >jitter? The PECL-to-TTL buffer which I am using, is adding lot's of
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