From: Brad Crowell (firstname.lastname@example.org)
Date: Thu Oct 12 2000 - 05:25:27 PDT
The best approach is to simulate your intended bus topology. The 10 ns prop
delay spec requires that the data be stable, no remianing significant
reflections. A simple calculation of trace delay doesn't account for
reflections that may cause your prop delay to be beyond the spec'ed 10 ns.
This approach was used (by others) to develop the Compact PCI spec and one I
have used recently. Although the trace delay was much smaller than 10 ns in
my design, there was a nasty reflection that caused the prop delay to
violate the spec! Better to deal with that in simulation than on a real
> -----Original Message-----
> From: email@example.com
> [mailto:firstname.lastname@example.org]On Behalf Of Doug Hopperstad
> Sent: Wednesday, October 11, 2000 4:34 PM
> To: 'email@example.com'
> Subject: [SI-LIST] : RE: PCI routing rules
> Does anyone have any information on PCI routing rules. I am trying to
> determine the maximum trace length between PCI devices and have been
> struggling with the 10nS time margin. Is there a formula to determine the
> maximum trace length between PCI devices?
> Doug Hopperstad
> QLogic Corporation
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