From: Bill Cohen (email@example.com)
Date: Tue Oct 10 2000 - 12:24:55 PDT
Todd Westerhoff wrote:
> Concerning HSTL (JEDEC EIA/JESD8-6):
> The standard specifies that the technology is "VDD independent" (makes
> sense, as long as the output buffers are properly designed), and that VDDQ
> supply should be in the range of 1.4 to 1.6 volts.
> Why then, are some vendors supplying parts that call for a 1.8 volt VDDQ
> supply and calling them HSTL?
The 1.8V VDDQ is to reduce power supplies on the board. Usually an ASIC
contains 3.3V (for LVTTL) and sometimes 2.5V (for SSTL). The core is run
at 1.8V for fast/low power logic. If another 1.5V voltage was added then
the chip would require 4 sepatate power supplies. If the HSTL was driven
at 1.8V then the core logic and HSTL I/O would be able to share the same
power supply. HSTL run at 1.8V can usually interface to 1.5V HSTL with
little trouble. Some adjustment of VREF may be necessary.
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