[SI-LIST] : Information on the I/O pads

About this list Date view Thread view Subject view Author view

From: Bo (bo_pfc@yahoo.com)
Date: Tue Oct 10 2000 - 09:51:16 PDT


Hi,

Recently I received models of the I/O pads from an ASIC vendor. Unfortunately
the models were encrypted and without any documentation. I have tried to get
documentation from the vendor but have been unable to. It seems that they have
used these pads from a third party and have no clue how the pads work. I would
be greatfull if someone could tell me what each pin might be. Here is the list
of all the pins:

GND VDD A DI LT PAD PADN RG RI TS VDD250 Z ZDI ZRI

I have made guess on these pins(it is differential buffer that I know):
GND - Ground
VDD - Power supply
A - Input to the pad from the core
PAD & PADN - Outputs from the pad to the package of the chip
VDD250 - Probably 2.5 Supply

TS - Probably something to do with tristating the buffer

Could someone please help me in determining what other pins represent. Any
answers or suggestions will be greatly appreciated.

Regards,
Bo

__________________________________________________
Do You Yahoo!?
Get Yahoo! Mail - Free email you can access from anywhere!
http://mail.yahoo.com/

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:29:42 PDT