Re: [SI-LIST] : Timing on a large board

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From: Michael Nudelman (mnudelman@tellium.com)
Date: Fri Oct 06 2000 - 10:23:03 PDT


Juergen,

How many stubs do you have on any given LVDS line on your backplane? If it is not
point-to-point, in the first place equalizing LVDS diff pairs on the board would be
a bad idea, since you want to keep stubs on your boards 1" or shorter. Again, only
if it is not point-to-point. Otherwise it's fine.

The 7ns difference would account for 42 (3.5 feet) inches, and you said your board
is roughly foot and a half. If the traces do not wiggle, and it is not some kind of
reflection you see - where the 7ns skew comes from? YOu should see no more than 3ns
skew worst case..

The driver of 10125 can drive 50 Ohm line; if you have space problem - use 75/100
Ohm lines (will make traces thinner and you could pack more of them), and since you
are point-to-point (TTL-to-LVDS input), use series termination; it will save you
instant drive current versus end-AC termination and power consumption versus
Thevenin split.

Mike.

Juergen Hannappel wrote:

> Hello,
>
> i have currently a design of a rather large board (400x366mm, a 9U VME
> Board) which has some problems with the overall timing of the signals
> involved. On the board i have 32 small modules (discriminators) with 2
> analog inputs and 3 digital outputs (TTL) each. The outputs are
> translated to LVDS via DS90C031 and then fed to 6 68-Pin connectors on
> the edge of the board in a way that for each discriminator module one
> differential pair goes to each of the output connectors. The total
> layout looks like this:
>
> C
> C I I I I I I I I
> C I I I I I I I I
>
> C I I I I I I I I
> C I I I I I I I I i
> C i
>
> The C's stand for the ouput connectors, the I's stand for the
> discriminator modules. The analog inputs come from a connector
> designated by the small i's in the drawing. Now the signal traces all
> have different lengths, and so the overall timing between different
> channels varies a lot, up to 7.5 ns are observed.
>
> In order to cure the weaknesses of this design i want to redo it,
> keeping the trace lengths all equal but there i run into trouble:
> Due to the high number of traces there is no space to build loops into
> the short ones, because they sit in the most crowded area of the
> board. Increasing the number of layers is also not feasible, because
> we have already 10 and the expense forbids more...
>
> So i thought to route the TTL signals (wich are only 3 times 32 single
> lines) instead of the LVDS signals (which are 6 times 32 pairs of
> lines) close to the output connectors, translate there from TTL to
> LVDS and terminate the TTL lines.
>
> Now my questions are:
> What impedance shall i choose to route the TTL lines? They are the
> output of MC10125 ECL to TTL translators, and operated al pulse
> lengths of 10 to 40 ns with rates of up to 5 MHz.
>
> Does such a design introduce more jitter? The jitter is a most
> important issue here and should be well below 100ps, if possible even
> below 50ps.
>
> Also, currently i use the DS90C031 as LVDS driver. How compares the TI
> SN65LVDS047 driver in terms of jitter?
>
> Thanks in advance,
> Juergen
>
> --
> Dr. Juergen Hannappel Office: W148 Phone: +49 228 73 2447 FAX +49 228 73 7869
> mailto:hannappel@physik.uni-bonn.de Physikalisches Institut der Uni Bonn
> http://lisa2.physik.uni-bonn.de/~hannappe Nussallee 12, D-53115 Bonn, Germany
> CERN: Phone: +412276 76461 Fax: 77930 Bat. 892-R-A13 F-01631 CERN CEDEX, France
>
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