From: Ken Cantrell ([email protected])
Date: Fri Oct 06 2000 - 10:03:43 PDT
Juergen,
Just a quick idea. If it is cost/time effective try using FPGA's as delay
lines on your re-layout.
Ken
-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of Juergen Hannappel
Sent: Friday, October 06, 2000 10:24 AM
To: [email protected]
Subject: [SI-LIST] : Timing on a large board
Hello,
i have currently a design of a rather large board (400x366mm, a 9U VME
Board) which has some problems with the overall timing of the signals
involved. On the board i have 32 small modules (discriminators) with 2
analog inputs and 3 digital outputs (TTL) each. The outputs are
translated to LVDS via DS90C031 and then fed to 6 68-Pin connectors on
the edge of the board in a way that for each discriminator module one
differential pair goes to each of the output connectors. The total
layout looks like this:
C
C I I I I I I I I
C I I I I I I I I
C I I I I I I I I
C I I I I I I I I i
C i
The C's stand for the ouput connectors, the I's stand for the
discriminator modules. The analog inputs come from a connector
designated by the small i's in the drawing. Now the signal traces all
have different lengths, and so the overall timing between different
channels varies a lot, up to 7.5 ns are observed.
In order to cure the weaknesses of this design i want to redo it,
keeping the trace lengths all equal but there i run into trouble:
Due to the high number of traces there is no space to build loops into
the short ones, because they sit in the most crowded area of the
board. Increasing the number of layers is also not feasible, because
we have already 10 and the expense forbids more...
So i thought to route the TTL signals (wich are only 3 times 32 single
lines) instead of the LVDS signals (which are 6 times 32 pairs of
lines) close to the output connectors, translate there from TTL to
LVDS and terminate the TTL lines.
Now my questions are:
What impedance shall i choose to route the TTL lines? They are the
output of MC10125 ECL to TTL translators, and operated al pulse
lengths of 10 to 40 ns with rates of up to 5 MHz.
Does such a design introduce more jitter? The jitter is a most
important issue here and should be well below 100ps, if possible even
below 50ps.
Also, currently i use the DS90C031 as LVDS driver. How compares the TI
SN65LVDS047 driver in terms of jitter?
Thanks in advance,
Juergen
-- Dr. Juergen Hannappel Office: W148 Phone: +49 228 73 2447 FAX +49 228 73 7869 mailto:[email protected] Physikalisches Institut der Uni Bonn http://lisa2.physik.uni-bonn.de/~hannappe Nussallee 12, D-53115 Bonn, Germany CERN: Phone: +412276 76461 Fax: 77930 Bat. 892-R-A13 F-01631 CERN CEDEX, France**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****
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