From: [email protected]
Date: Wed Oct 04 2000 - 17:08:39 PDT
Ken,
Point your browser to:
http://developer.intel.com/design/chipsets/designex/298233.htm?iid=PCG+side&
This is a pointer to the Intel 815 Chipset Platform Design Guide. This is
now a public document. The 815 is Intel's first chipset to support PC133.
These guidelines can give you a general feel for routing topologies, etc.
However, keep in mind that much of a memory bus solution for a given
platform can be dependent upon the given chipset that you are using. To my
knowledge there isn't really a "generic" set of PC133 recommendations for
the board level (the DIMMs themselves are of course well defined and
spec'd).
For example, one vendor's chipset may provide 2 full copies of
address/command signals so if you have two DIMMs you can send 1 copy to each
DIMM and therefore each I/O buffer is only driving 1 DIMM worth of load.
However, another chipset vendor may, due to cost or pin count concerns, only
provide 1 copy of address and you must drive both DIMMs with that one copy.
Therefore each address/cmd I/O ends up driving 2 DIMMs worth of loads.
These two cases would probably end up with different length routing
requirements (and obviously different topologies). The same case can made
for multiple or single copies of CS# and CKE.
Also, often times, your routing constraint actually ends up being driven by
the read path (i.e. read cycles as opposed to write cycles). And here
again, different chipset vendors may have different internal timing
characteristics on their read paths. This can result in a wide range of
setup and hold time requirements at the pin of the memory controller for a
read cycle. So a particular layout that gives you positive timing margin
with chipset A could in fact result in negative timing margins (at least in
worst case "simulation land") if used with chipset B due to completely
different timing parameters for the memory controller. Again, this is
mainly on read cycles. Setup and hold (and other timing parameters) are
pretty well defined at the SDRAM devices themselves (for write cycles).
Well this may be more than you ever wanted to know! I believe the document
I've mentioned above can give you a general sense of placement, approximate
lengths, possible topologies, etc. But keep in mind that there are other
layout guidelines for other chipsets out there that would be different from
the ones you'll see in the Intel document.
I've worked on memory interfaces for a couple of years now and I continue to
be amazed at how challenging it can be to really layout a robust memory
channel. Even on plain old vanilla SDRAM. There are so many variables. Do
you have two DIMM slots or three? Are you using DIMMs with x8 devices or
x16? Double sided or single sided? Which chipset? (timing parameters such
as Tco, setup & hold, etc. can be different for different chipsets) Are you
supporting both registered or unbuffered DIMMs or both?
Every once in awhile on a rough day I long to work on a point to point bus!
Let me know if I can be of any further help.
Regards,
Jim P.
Jim Pankratz
Dell PSG Signal Integrity Group
512.723.5357
[email protected]
-----Original Message-----
From: Ken Egan [mailto:[email protected]]
Sent: Wednesday, October 04, 2000 4:31 PM
To: silist
Subject: [SI-LIST] : 133 SDRAM guidelines
Just wondering if there was any kind of guideline for motherboard designs
for 133 MHz SDRAM,i.e. circuit topologies , maximum trace lenght from memory
controller to DIMM's...
Thanks
Ken Egan
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