From: Thomas Jackson (firstname.lastname@example.org)
Date: Wed Oct 04 2000 - 18:53:14 PDT
My suggestion is to proportion the total power plane area to the currents.
You estimate the area of one plane layer, pick how many planes you want,
calculate the plane areas for each voltage, and check if the resulting plane
areas are large enough for the parts. If the area for one voltage is
smaller than the sum of the areas of the parts using this voltage, you have
a problem. This is not an exact science, but it quickly gives you a lower
bound on the number of voltage planes necessary.
Thomas L. Jackson, P.E.
Staff Product Development Engineer
Network Access Development
Systems Solutions Group
FUJITSU MICROELECTRONICS, INC.
3545 North First Street
San Jose, CA 95134-1804
telephone: (408) 922-9574
facsimile: (408) 922-9618
From: Jeff Reeve [mailto:email@example.com]
Sent: Wednesday, October 04, 2000 5:14 PM
Subject: [SI-LIST] : multiple power planes
I apologize in advance if this issue has been beat to death already...but
here it goes....
I have a board with multiple power rails 12V, 5V, 3.3V, 2.5V and 1.8V. It
seems like overkill to make separate power/gnd planes for each of the
voltages...sheesh 10 planes to handle power! So what are you guys out there
doing to limit the number of planes and yet still maintain low EMI? I would
like to implement in the least planes possible and maintain 50-55 ohm
impedance. Signal rates will be up to 100MHz. 1.8V will carry up to 8A, 2.5V
will carry up to 6A, 3.3V will carry up to 4A, 5V will carry up to 8A and
12V will be less than 1.5A. Typical devices on this board are FPGAs, SDRAM,
RiscProcessor, Multi-media Processors, 10/100 Ethernet chip sets, SCSI chip
sets, IDE chipsets, USB chipsets, etc. Anybody willing to share recommended
Any advice and other pearls would be most appreciated!
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