From: sweir ([email protected])
Date: Fri Sep 29 2000 - 01:39:31 PDT
Definitely push the power and ground planes together. Also, make sure that
the vias for your bypass caps are as close to the capacitor pads as
possible. Both of these measures fight the evil inductance monster that
dominates your high frequency impedance.
The antiresonance needs to be watched, but as you might have divined from
reasonable recent postings, the most important issue is to maintain really
low impedance at harmonics of coherent signals, which tend to be clocks.
The problem with series resistors is the series inductance that comes along
for the ride. If you have peaks in bad places, change the capacitor
values, or use more discrete values to flatten the peaks out. From the
sound of it, I don't think you do. Given the distance from the surface to
your planes, I think only the 150MHz is likely to be within the range of
antiresonance with the discrete caps, and then only for devices 1000pF or
smaller in 0603 or smaller packages. Good luck.
At 05:42 PM 9/29/00 +1100, you wrote:
>Si-List <[email protected]>
I have a question regarding plane bypassing.
We have a board measuring 277 x 160mm which is a 4 layer board. With a
near field probe I can quite easily pick up noise from its exit cables
which seems to be fairly prominent at around 150, 300 and 500MHz.
I have done a two port network analyser sweep of the power plane which
reveals peaks near the frequencies listed above (no surprise) The board
has ground copper fill top and bottom and I have measured the plane
capacitance of the raw board at about 5nF (planes are assumed to be
0.5mm apart) The board has a number of 100nF and 10nF capacitors spread
across the board and a couple of tantalums for bulk charge.
Interesting (?) thing is that if I sweep a raw board without any bypass
capacitors, the insertion loss plot looks almost idential above about
I can go to 0.1mm (4mil) plane spacing without impacting cost. Without
extra copper fills this should give about 16nF of plane capacitance. I
have done some basic simulation with "real" capacitors which reveals
problems with parallel resonance peaks. I can damp them by adding a
small resistance (approx 1 ohm) in series with each capacitor.
Can anyone give me some practical advice here, particularly in view of
adding series resistance to control parallel resonances caused by the
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