[SI-LIST] : Another plane bypass question...

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From: Bryan Ackerly ([email protected])
Date: Thu Sep 28 2000 - 23:42:19 PDT

I have a question regarding plane bypassing.

We have a board measuring 277 x 160mm which is a 4 layer board. With a
near field probe I can quite easily pick up noise from its exit cables
which seems to be fairly prominent at around 150, 300 and 500MHz.

I have done a two port network analyser sweep of the power plane which
reveals peaks near the frequencies listed above (no surprise) The board
has ground copper fill top and bottom and I have measured the plane
capacitance of the raw board at about 5nF (planes are assumed to be
0.5mm apart) The board has a number of 100nF and 10nF capacitors spread
across the board and a couple of tantalums for bulk charge.

Interesting (?) thing is that if I sweep a raw board without any bypass
capacitors, the insertion loss plot looks almost idential above about

I can go to 0.1mm (4mil) plane spacing without impacting cost. Without
extra copper fills this should give about 16nF of plane capacitance. I
have done some basic simulation with "real" capacitors which reveals
problems with parallel resonance peaks. I can damp them by adding a
small resistance (approx 1 ohm) in series with each capacitor.

Can anyone give me some practical advice here, particularly in view of
adding series resistance to control parallel resonances caused by the
plane capacitance?

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