RE: [SI-LIST] : EDC Input Impedence

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From: Charbonneau, Richard A (CharbRA@LOUISVILLE.STORTEK.COM)
Date: Tue Sep 26 2000 - 16:01:56 PDT


-----Original Message-----
From: Ray Anderson [mailto:Raymond.Anderson@eng.sun.com]
Sent: Tuesday, September 26, 2000 3:28 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : EDC Input Impedence

A couple of comments on the plot that was attached:

1)
With the linear frequency scan the portion of the curve that
shows the capacitive behavior is compressed over into the left
1/8" of the plot. Using a log frequency axis is a lot more
instructive when looking at the low end of the freq. range.

I agree..please see attached plot below 500MHz

2)
The various slopes on the traces indicate differing inductive
components past resonance, most likely from varying stackup
thicknesses.

The boards had parts mounted on them including 33, 0.01 uF capacitors.

3)
Note that the higher order resonances are much more pronounced
for some of your traces (FR4 being the worst) compared to others
(C-Ply being the best). Again I think this is due to the
variations in stackup thicknesses of the samples. Thin dielectrics
tend to suppress the higher frequency impedance excursions
amplitudes.

You are correct..the C-Ply 0.3 mils thick

Any idea what the geometries were that the UMR people were using ???

-Ray

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