RE: [SI-LIST] : EDC Input Impedence

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From: Charbonneau, Richard A (CharbRA@LOUISVILLE.STORTEK.COM)
Date: Tue Sep 26 2000 - 15:38:32 PDT


Here is the stack-up for the printed wiring board. The table (below Figure
1)shows the dielectric thickness of the various materials used between
pwr/gnd. The main point is that the input impedence is below 4 ohms at
5GHz. Dr. Hubing has attributed this to the inductance of the SMA connector
that was used and has said that the impedence of the power bus is much lower
than shown. -RC

-----Original Message-----
From: Ray Anderson [mailto:Raymond.Anderson@eng.sun.com]
Sent: Tuesday, September 26, 2000 3:28 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : EDC Input Impedence

> I have attached a plot showing the input impedence for a variety of
buried
> capacitance materials (courtesy UMR).

A couple of comments on the plot that was attached:

1)
With the linear frequency scan the portion of the curve that
shows the capacitive behavior is compressed over into the left
1/8" of the plot. Using a log frequency axis is a lot more
instructive when looking at the low end of the freq. range.

2)
The various slopes on the traces indicate differing inductive
components past resonance, most likely from varying stackup
thicknesses.

3)
Note that the higher order resonances are much more pronounced
for some of your traces (FR4 being the worst) compared to others
(C-Ply being the best). Again I think this is due to the
variations in stackup thicknesses of the samples. Thin dielectrics
tend to suppress the higher frequency impedance excursions
amplitudes.

Any idea what the geometries were that the UMR people were using ???

-Ray

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