RE: [SI-LIST] : No buried/embedded capacitance?

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From: Greim, Michael ([email protected])
Date: Fri Sep 22 2000 - 13:00:57 PDT

Hi John,

It's not uncommon to see anti-resonance peaks in the
power system between the resonance valleys in your
PDS. I have most often seen them between bulk and
chip cap regions and then again between chip caps and
plane capacitance.

What you might want to try is mixing capacitance values
instead of putting all your eggs in the .1 uF basket.
remember that impedance is halved as the number of caps
is doubled. You may have reached your point of diminishing
returns well below 321 caps. I would recommend rerunning
your sims with some values of 47 nF, 10 nF and 4.7nF. I
suspect that you will see a much better impedance across

Also keep in mind that all of this is assumes that the
capacitors are mounted to the circuit board in an appro
priate manner. A very low ESR cap mounted through a
High L path will cause bad things to happen with your

Best of Luck

Michael Greim

-----Original Message-----
From: John Kennedy [mailto:[email protected]]
Sent: Friday, September 22, 2000 2:00 PM
To: silist
Subject: [SI-LIST] : No buried/embedded capacitance?

Dear All,

I have a board that through analysis requires:

32 x 100 microfarad caps with inductance of 4nH and 0.1 ohms ESR, for
bulk capacitance.
321 x 100nF caps with inductance of 1nH (using 0508 package) and ESR of
0.1 ohms for high frequency switching of 576 sram drivers. I have an
Fknee of 200 MHz.

If I plot this using Ultracad's software ( ) I get the black plot in the attached
image. You can see that the maximum impedance is below my goal of 0.004
ohms at 200 MHz.

I then added to the analysis the use of either buried capacitance using
a standard dielectric of 4.5 with thickness of 2 mil (the red plot), and
then using embedded capacitance using Hadco's dielectric of 50 with a
thickness of 2 mil (the blue plot). Assumed inductance was 1 pH and 0.1
micro ohms ESR.

As you can see in both cases it appears to me that buried or embedded
capacitance is a hindrance and therefore I should separate my power and
ground planes with signal layers. My question to you all is am I
correct in this statement or have I missed something?

Many thanks,


PS. 321 ceramic caps is a lot of board space, any suggestions on ways to
reduce the count?

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