From: Bill Owsley (email@example.com)
Date: Fri Sep 22 2000 - 12:48:04 PDT
Possibly he is including the inductance of mounting the caps... Although
the listing of a 0508 vs 0805 caps implies some effort at reducing the
inductance, that may not have included traces and vias.
At 12:04 PM 09/22/2000 -0700, Muhammad S. Sagarwala wrote:
>0508 caps with 1nh ESL????I am looking at the AVX specs and they list the
>ESL to be 0.6nh.
>I am pretty sure Murata specs them to be less than 1nh too...I would
>recommend checking the
>ESL spec. again...
>From: John Kennedy <firstname.lastname@example.org>
>To: silist <email@example.com>
>Date: Friday, September 22, 2000 11:24 AM
>Subject: [SI-LIST] : No buried/embedded capacitance?
> >Dear All,
> >I have a board that through analysis requires:
> >32 x 100 microfarad caps with inductance of 4nH and 0.1 ohms ESR, for
> >bulk capacitance.
> >321 x 100nF caps with inductance of 1nH (using 0508 package) and ESR of
> >0.1 ohms for high frequency switching of 576 sram drivers. I have an
> >Fknee of 200 MHz.
> >If I plot this using Ultracad's software (
> >http://www.ultracad.com/esr.htm ) I get the black plot in the attached
> >image. You can see that the maximum impedance is below my goal of 0.004
> >ohms at 200 MHz.
> >I then added to the analysis the use of either buried capacitance using
> >a standard dielectric of 4.5 with thickness of 2 mil (the red plot), and
> >then using embedded capacitance using Hadco's dielectric of 50 with a
> >thickness of 2 mil (the blue plot). Assumed inductance was 1 pH and 0.1
> >micro ohms ESR.
> >As you can see in both cases it appears to me that buried or embedded
> >capacitance is a hindrance and therefore I should separate my power and
> >ground planes with signal layers. My question to you all is am I
> >correct in this statement or have I missed something?
> >Many thanks,
> >PS. 321 ceramic caps is a lot of board space, any suggestions on ways to
> >reduce the count?
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Bill Owsley, email@example.com
7025 Kit Creek Road
RTP. NC. 27709
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