From: Larry Smith ([email protected])
Date: Fri Sep 22 2000 - 12:18:08 PDT
John - Don't separate your power planes! The advantages that you get
from thin dielectric between power planes always helps you: Increased
capacitance and reduced inductance.
The problem is in the model that you have used for the power planes.
At frequencies over 100 MHz, lumped components are not good enough.
There is a time delay between discrete subsections of the power planes
that is not negligible compared to 1/100MHz.
The peaks shown in your simulations are due to the inductance of the
discrete capacitors resonating with the pure capacitance of the power
planes. This is a very real phenomenon, measurable in the lab. The
peaks can be dramatically reduced by choosing some low valued capacitors
that are resistive (ESR) at the critical frequencies rather than
inductive. That reduces the Q of the high Q circuit.
But, other resonances crop up due to the size of the power plane
cavity. You need a power plane simulator to see these.
Another factor is skin effect. The planes are far more resistive at
100MHz and 1GHz than you have modeled. Only the skin of the copper
planes is conductive. This greatly reduces the Q and therefor the
peaks shown in the simulation.
Bottom line is that you need a plane simulator that accounts for the
distributed nature and the frequency dependent loss of the power planes
to do power distribution analysis above 100 MHz.
> Date: Fri, 22 Sep 2000 10:59:54 -0700
> From: John Kennedy <[email protected]>
> X-Accept-Language: en
> MIME-Version: 1.0
> To: silist <[email protected]>
> Subject: [SI-LIST] : No buried/embedded capacitance?
> Dear All,
> I have a board that through analysis requires:
> 32 x 100 microfarad caps with inductance of 4nH and 0.1 ohms ESR, for
> bulk capacitance.
> 321 x 100nF caps with inductance of 1nH (using 0508 package) and ESR of
> 0.1 ohms for high frequency switching of 576 sram drivers. I have an
> Fknee of 200 MHz.
> If I plot this using Ultracad's software (
> http://www.ultracad.com/esr.htm ) I get the black plot in the attached
> image. You can see that the maximum impedance is below my goal of 0.004
> ohms at 200 MHz.
> I then added to the analysis the use of either buried capacitance using
> a standard dielectric of 4.5 with thickness of 2 mil (the red plot), and
> then using embedded capacitance using Hadco's dielectric of 50 with a
> thickness of 2 mil (the blue plot). Assumed inductance was 1 pH and 0.1
> micro ohms ESR.
> As you can see in both cases it appears to me that buried or embedded
> capacitance is a hindrance and therefore I should separate my power and
> ground planes with signal layers. My question to you all is am I
> correct in this statement or have I missed something?
> Many thanks,
> PS. 321 ceramic caps is a lot of board space, any suggestions on ways to
> reduce the count?
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