[SI-LIST] : No buried/embedded capacitance?

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From: John Kennedy (john.kennedy@cppus.com)
Date: Fri Sep 22 2000 - 10:59:54 PDT


Dear All,

I have a board that through analysis requires:

32 x 100 microfarad caps with inductance of 4nH and 0.1 ohms ESR, for
bulk capacitance.
321 x 100nF caps with inductance of 1nH (using 0508 package) and ESR of
0.1 ohms for high frequency switching of 576 sram drivers. I have an
Fknee of 200 MHz.

If I plot this using Ultracad's software (
http://www.ultracad.com/esr.htm ) I get the black plot in the attached
image. You can see that the maximum impedance is below my goal of 0.004
ohms at 200 MHz.

I then added to the analysis the use of either buried capacitance using
a standard dielectric of 4.5 with thickness of 2 mil (the red plot), and
then using embedded capacitance using Hadco's dielectric of 50 with a
thickness of 2 mil (the blue plot). Assumed inductance was 1 pH and 0.1
micro ohms ESR.

As you can see in both cases it appears to me that buried or embedded
capacitance is a hindrance and therefore I should separate my power and
ground planes with signal layers. My question to you all is am I
correct in this statement or have I missed something?

Many thanks,

John

PS. 321 ceramic caps is a lot of board space, any suggestions on ways to
reduce the count?


cap.gif

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