RE: [SI-LIST] : parasitic value for via

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From: Ozgur Misman (omism@amkor.com)
Date: Sat Sep 16 2000 - 16:10:30 PDT


Hello Pierre,
I enjoyed your visualization. However, I think the factor of 2 is coming from
the fact that the seperation between the plates in your description is not d2-d1
rather it is r2-r1. r2=d2/2 and r1=d1/2. If you redo the calculation using
r2-r1 as plane seperation rather then d2 -d1 you will have an extra factor of 2
in the nominator. Then you will see your calculation will be consistent with
Johnson's.

Best Regards,
Ozgur Misman
Sr. Engineer

Pierre-Luc Cantin <plcantin@hyperchip.com> on 09/16/2000 03:23:08 PM

Please respond to Pierre-Luc Cantin <plcantin@hyperchip.com>
                                                              
                                                              
                                                              
 To: "'si-list@silab.eng.sun.com'"
          <si-list@silab.eng.sun.com>,
          "'chlee99@samsung.co.kr'" <chlee99@samsung.co.kr>
                                                              
 cc:
                                                              
                                                              
                                                              
 Subject: RE: [SI-LIST] : parasitic value for via
                                                              

Hello Chunho Lee,

I made once the effort to demonstrate Johnson via capacitance my-myself,
here is my demonstration and conclusion

- picture the via being a cylinder diameter=D1
- picture a second cylinder wrapped around the first one D2>D1
     - this second one represents power/gnd planes
- both cylinders are iso-potential
- un-fold both cylinders and you end up with two parallel plates.
     - the separation between the plates is the via clearance
1270-711(D2)
     - the height of both cylinders is the board thickness (T)
     - the width of the cylinder is the via circumference times
pi=3.1416... (pi*D1).

Now let do the math using Johnson example as a reference:

- er=4.7
- T=63mil ---> 1600um
- D1=28mil ---> 711um
- D2=50mil ---> 1270um

....Cvia = 1.41*4.7*0.063*0.028/(0.050-0.028) = 0.53pF

Now using two parallel plates capacitance formula:

Cvia= er*eo*A/d = er*eo*T*D1*pi/(D2-D1), eo=8.85aF/um

= 8.85aF/um*4.7*1600um*711um*pi/(1270um-711um)
= 265795aF = 0.265pF

Now here is something curious, if we then multiply again by 2

Cvia = 0.531pF !!! bang on

Assuming my demonstration process is fine,
have they assumed the circumference is 2*pi*diameter?
----------------------------------------------------------------------------
--------------------------

Pierre-Luc Cantin
Sr. ASIC Designer /
SI Team Leader

plcantin@hyperchip.com
www.Hyperchip.com

phone (514) 931-5335 x217
fax. (514) 931-9923

COME MEET US AT:

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-----Original Message-----
From: owner-si-list@silab.eng.sun.com
[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of
chlee99@samsung.co.kr
Sent: Saturday, September 16, 2000 1:08 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : parasitic value for via

Hello everyone.

I am looking for parasitic value for via.
and Dr Johnson's derivation is ...

  C=[1.41*Er*T*D1]/[D2-D1]
 where D2= diameter of clearance hole in GND plane,
       D1= diameter of pad surrounding via,
       T = thickness of PCB,
       Er= permeability.

parasitic inductance of via :
  L= 5.08h[ln(4h/d)+1]
 where h= length of via,
       d= diameter of via.

Let me explain
How this equation is derived?

thanks.

**********************************************
 Chunho Lee,
 Senior Engineer,

 SAMSUNG ELECTRONICS CO.,
 E-CIM, Management Innovation Team,
 416, Maetan-3dong, Paldal-gu,
 Suwon city, Korea
 Tel : 82-31-200-3097
 email: chlee2@samsung.co.kr
**********************************************

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