RE: [SI-LIST] : DDR SDRAM DQS vs DQ

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From: Weber Chuang (WeberChuang@via.com.tw)
Date: Wed Sep 06 2000 - 18:49:53 PDT


hi Ken,

  Because they would like to leave all the DLL stuff to chipset(Dram
controller).

  Best Regards
    Weber Chuang( e)
 Signal & Timing Integrity Engineer,
 VIA Technologies, Inc. Taipei, Taiwan, ROC
 TEL : 886-2-22185452 ext : 6522
 mailto:weber@via.com.tw
 http://www.via.com.tw
 Very Innovative Architecture

-----Original Message-----
From: Ken Wu [mailto:ken@force10networks.com]
Sent: Thursday, September 07, 2000 8:59 AM
To: 'si-list@silab.eng.sun.com'
Subject: [SI-LIST] : DDR SDRAM DQS vs DQ

Can anyone tell me why JEDEC specifies in DDR SDRAM spec that DQS is
edge-aligned
with data when reading from SDRAM, while center-aligned with data when
writing to SDRAM?
I don't see any reason why SDRAM cannot send out data with center-aligned
strobe.

Regards,

Ken

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