RE: [SI-LIST] : DDR SDRAM DQS vs DQ

About this list Date view Thread view Subject view Author view

From: Weber Chuang ([email protected])
Date: Wed Sep 06 2000 - 18:49:53 PDT


hi Ken,

  Because they would like to leave all the DLL stuff to chipset(Dram
controller).

  Best Regards
    Weber Chuang( �����e)
 Signal & Timing Integrity Engineer,
 VIA Technologies, Inc. Taipei, Taiwan, ROC
 TEL : 886-2-22185452 ext : 6522
 mailto:[email protected]
 http://www.via.com.tw
 Very Innovative Architecture

-----Original Message-----
From: Ken Wu [mailto:[email protected]]
Sent: Thursday, September 07, 2000 8:59 AM
To: '[email protected]'
Subject: [SI-LIST] : DDR SDRAM DQS vs DQ

Can anyone tell me why JEDEC specifies in DDR SDRAM spec that DQS is
edge-aligned
with data when reading from SDRAM, while center-aligned with data when
writing to SDRAM?
I don't see any reason why SDRAM cannot send out data with center-aligned
strobe.

Regards,

Ken

**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****

**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected]. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:29:27 PDT