Re: [SI-LIST] : DDR SDRAM DQS vs DQ

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From: Scott McMorrow (scott@vasthorizons.com)
Date: Wed Sep 06 2000 - 18:14:05 PDT


Ken,

It is easier (read cheaper) to edge allign DQS in the SDRAM. To do otherwise
would require a DLL for output timing control in SDRAM. Since there are many
more DDR SDRAM in a system than controllers, it was decided to place the
burden of clocking allignment on the Controller. This reduces the cost of the
DRAM at the expense of complexity in the controller.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

Ken Wu wrote:

> Can anyone tell me why JEDEC specifies in DDR SDRAM spec that DQS is > edge-aligned > with data when reading from SDRAM, while center-aligned with data when > writing to SDRAM? > I don't see any reason why SDRAM cannot send out data with center-aligned > strobe. > > Regards, > > Ken > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > si-list archives are accessible at http://www.qsl.net/wb6tpu > ****

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****


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