Re: [SI-LIST] : length constraints in Specctraquest

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From: Lalit Shinde (lalit@cadence.com)
Date: Tue Sep 05 2000 - 09:28:37 PDT


Note that applying topologies back into SPECCTRAQuest
with constraints across resistors will not work in 13.6
production release. You will need 14.0 release for that.

Lalit Shinde wrote:
>
> Hi Aloke,
>
> Here is how you can do it.
> - Go to Constraint dialog box, Delay tab
> - Select Driver, it's name appears as pin1
> - Select Receiver, it's name appears as pin2.
> - Change Rule Tpe from 'Delay' to 'Length'
> - Enter min and max constraint values.
> - Add the constraint rule.
> Note that it does not matter how many TLines/Traces
> are there between pin1 and pin2.
> - Similarly go to Match-Delay tab and add constraint.
> Make the scope Global so that it applies to all
> bits of bus.
>
> Now you can drive it back into Allegro/SPECCTRAQuest.
> Note that you can also add these constraints in
> Allegro/SPECCTRAQuest as well.
>
> Aloke Bhattacharya wrote:
> >
> > Hello,
> > I have a simple topology like this:
> >
> > Driver ------TL1---------/\/\/\/\-------TL2----------Receiver
> > 33ohm
> >
> > The driver is connected to the receiver through a 33ohm series
> > termination resistor. This Xnet is a part of
> > a group of source synchronous signals and I need to apply the following
> > constraints to the above topology in Sigxp:
> > (i) the length of (TL1+TL2) has to match across all the signals within
> > 50 mils.
> > (ii)TL1+TL2 length should be between 1 inch and 6 inches
> >
> > In the set constraints menu of Sigxp, I don't see any option of applying
> > delay or matched delay constraints
> > to the sum of lengths of two or more transmission lines. Currently I am
> > able to apply the delay or the matched delay constraint to only a single
> > segment of a transmission line(like TL1 or TL2 in the above diagram).
> > Does anybody know how to assign such a constraint in Sigxp? If it is not
> > possible to assign it in Sigxp, is it possible to do it in Allegro?
> >
> > With regards,
> > Aloke
> >
> > --
> > **********************************************************************
> > * Aloke Bhattacharya, *
> > * Senior Engineer-VLSI/System Design,
> > * *
> > * Wipro Infotech, *
> > * Global R&D, *
> > * 88, M.G. Road, 5th Floor, *
> > * S.B. Towers, *
> > * Bangalore- 560 001 , *
> > * INDIA *
> > * Tel : 91-80-5588422(Ext. 520) *
> > * email: aloke.bhattacharya@wipro.com
> > * *
> > **********************************************************************
> >
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>
> --
> Regards,
> -Lalit.
> 978-262-6475.
>
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-- 
Regards,
-Lalit.
978-262-6475.

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