[SI-LIST] : Q3'00 Intel Technology Journal on-line: packaging issue

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From: Polka, Lesley A (lesley.a.polka@intel.com)
Date: Tue Aug 29 2000 - 14:27:06 PDT


All --- The Q3'00 Intel Technology Journal was published last week on-line
at Intel's Developers' web page ( http://developer.intel.com/technology/itj/
). This quarter's issue is devoted to microprocessor packaging at Intel, so
I thought I'd let this newsgroup know of its publication since the topic is
probably of interest to newsgroup members. The seven papers in the issue
were authored by technical content experts at Intel who work on technology
development for Intel's packaging, assembly and test processes. The papers
included in the issue are:
  
1. The Evolution of Microprocessor Packaging
2. Flip-Chip Technology on Organic Pin Grid Array Packages
3. Package-Level Interconnect Design for Optimum Electrical Performance
4. Thermal Performance Challenges from Silicon to Systems
5. Simultaneous Chip-Join and Underfill Assembly Technology for Flip-Chip
Packaging
6. A Mechanism-Based Methodology for Processor Package Reliability
Assessments
7. Thermal Challenges During Microprocessor Testing

Each paper contains author contact information for specific questions
related to the subject material.

                                        --- Lesley Polka
                                            Staff Engineer, Intel
Corporation

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