From: Ritchey Lee (email@example.com)
Date: Wed Aug 23 2000 - 08:37:58 PDT
I design lots of high speed multilayer PCBs. I use 3 mils between power planes to achieve maximum plane capacitance. You can do this reliably so long as you do you stackup so that the dielectric between the power planes is the prepreg material.
Barry Ma wrote:
> Thanks a lot for your great note! It is very helpful.
> You mentioned small spacing between pwr and gnd planes in the PCB a couple of times in the discussion. I'd like to add my 2 cents.
> In addition to enough capacitance between pwr and gnd planes for high frequencies noise to go through, the small spacing also makes it possible for limited decoupling capacitors to be shared by different gates. This is another important reason why much less numbers of decap can practically work than calculated numbers.
> You suggested 5 mil or so spacing, Prof. Todd Hubing asked for at least < 10 mil. Is there any articles giving quantitative description about the criteria?
> Best Regards,
> Barry Ma <firstname.lastname@example.org>
> ANRITSU www.anritsu.com
> Morgan Hill, CA 95037
> Tel. 408-778-2000 x 4465
> Free Unlimited Internet Access! Try it now!
> **** To unsubscribe from si-list or si-list-digest: send e-mail to
> email@example.com. In the BODY of message put: UNSUBSCRIBE
> si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
**** To unsubscribe from si-list or si-list-digest: send e-mail to
firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Tue May 08 2001 - 14:29:19 PDT