RE: [SI-LIST] : Why CML for high-speed interfaces?

From: Zabinski, Patrick J. ([email protected])
Date: Mon Aug 21 2000 - 05:43:47 PDT

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>
> Oops; another brain-cramp.
>
> In ECL, the total power dissipation would be:
>
> P = V^2 / R
> = (VCC-VTT)^2/Rterm
> = 2.0^2/50
> = 80 mW
>
> That's per single ended signal. For a diff pair,
> power would be 2 * 80 = 160 mW.
>
>

It must be too early for me this morning...

The current through the termination resistor
is (2.0 - 0.8)/50 = 24 mA for a high and
(2.0-1.8)/50 = 4 mA for a low. The average
current is (24 + 4)/2 = 13 mA.

So, the power dissipated by the resistor
and transistors is:

        <P> = (VCC-VTT) * <I>
          = 2.0 * 13mA
          = 26 mW (per side)

        or, 52 mW total.

Again:
        P(ECL) = 52 mW (nominal case)
        P(CML) = 40 mW (worst case)

So, P(ECL) > P(CML).

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