# RE: [SI-LIST] : Why CML for high-speed interfaces?

From: Zabinski, Patrick J. ([email protected])
Date: Mon Aug 21 2000 - 05:20:59 PDT

Selva,

> Can you explain little bit more on power consumption of PECL
> & CML with
> equations? Which is better?
>

Oops; another brain-cramp.

In ECL, the total power dissipation would be:

P = V^2 / R
= (VCC-VTT)^2/Rterm
= 2.0^2/50
= 80 mW

That's per single ended signal. For a diff pair,
power would be 2 * 80 = 160 mW.

For CML, the total voltage drop is VCC-VEE, and the
current is dictated by the technology you happen to
be using, which generally ranges from 3 to 8 mA. So,
power would be:

P = V * I
= (VCC-VEE) * IEE
= 5 * 0.008 (worst case; most often better)
= 40 mW

Because common CML implementations force the current
(8 mA) through either the true or complement, there is no
need to double the power dissipation.

So, P(ECL) = 80 mW
P(CML) = 40 mW

i.e., P(ECL) >= 2 * P(CML)

(did I get it right this time?)

> It will be better if you give any information on CML(like app notes..)
>

I don't know of any app notes, but here are two references

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
TITLE DC Analysis of Current Mode Logic
SOURCE IEEE Circuits and Devices Magazine
DATE March, 1989
PAGES 21-35

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
TITLE High-Speed InP HBT Circuits, Chapter 8
AUTHOR J. F. Jensen, L. M. Burns, and W. E. Stanchina
DATE 1995?
PAGES 265-315
(I got a preliminary copy of this chapter before
publication, and I never did find out who published
it, copyright date, ISBN, etc. However, if
you work with CML, this chapter is pretty useful.

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