From: selvaraj subramanian ([email protected])
Date: Sun Aug 20 2000 - 21:23:05 PDT
I have gone through your explanation about PECL & CML. It was nice.
Can you explain little bit more on power consumption of PECL & CML with
equations? Which is better?
I am also not able to follow the return current paths in your last
It will be better if you give any information on CML(like app notes..)
----- Original Message -----
From: Zabinski, Patrick J. <[email protected]>
To: <[email protected]>
Sent: Friday, August 18, 2000 5:19 PM
Subject: RE: [SI-LIST] : Why CML for high-speed interfaces?
> I'll take a stab at this, but first, when you say "PECL", I'm
> assuming differential, not single-ended.
> I might be taking the subtleties too far, but I consider
> CML to be 'truly differential' where PECL is 'complementary'.
> If you look at a CML driver, the two open collector transistors
> are tied to a common, constant current source. As a result,
> the total current being sourced by these two transistors is
> a constant DC level. If one transistor sources more current, the
> other transistor is forced to source less. In this manner, the
> two outputs are forced to complement one another.
> In PECL, the two drive transistors are controlled separately,
> so their total current is not always a constant level, particularly
> during bit transitions. As such, you can have situations where
> both signals are high, or both are low, or the track states
> okay but their swings and/or transitions do not match.
> This difference in what I like to term "differential vs complementary"
> is subtle for good PECL designs with very good matching between
> the + and - signals, but in reality, PECL drivers will
> produce some dI/dt noise due to imbalances between the signals
> (much more than CML, but much less than single ended full-swing).
> Also, because the + and - signals of CML are tied-at-the-hip
> (okay, at the emitter), the action of one transistor helps
> the other to react, so the end result is that you'll have
> equal fall and rise times even if the transistors
> and loads are not equal (not generally the case in PECL),
> and the edge rates will be faster due to the push-pull
> reaction between them.
> CML and PECL are both power hungry (compared to several
> other interfaces), but CML is generally less. PECL drivers
> consume approximately 1.4V^2 / 50 = 39 mW per side (1.4V = average
> of 0.8 and 1.8 V drop of Vhi and Vlo). In CML, you must
> look at the constant current source (generally 3 to 4
> mA) times the supply voltage (3.3V), which equates to
> ~10 mW per both sides.
> On the receiver end, the designs in practice are generally
> about equal in performance. I think the real difference
> is in the driver.
> One additional subtlety: you mentioned "PECL" vs "ECL". In
> PECL, the return currents go through the positive VCC supply
> and the termination VTT supply, not the ground VEE supply.
> In most designs I've seen (and you'll see it a lot in this
> reflector) Ground is considered King amongst all other concerns
> while VCC and VTT are considered less important. If you're
> trying to push and optimize a PECL-based design, GND should be
> considered second-fiddle to VCC and VTT. This is difficult
> for some to understand and believe, so most often PECL is
> misused. On the other hand, CML's return current is through
> GND, which makes it more suitable to the casual user. CML
> also only relies on one return supply (GND), not two like
> PECL (VCC and VTT), makes board stackup easier. Note, "ECL"
> is a bit better than "PECL" in that at least one of its
> return paths is GND.
> > I have noticed that many new high-speed interfaces are using
> > current-mode logic (CML).
> > Are there any particular advantages for high-speed signaling
> > with CML as
> > compared to, say, PECL? Driver design? receiver noise
> > immunity? Lower
> > power dissipation? Etc.
> > -Eric
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