[SI-LIST] : Free NetSeminar - "Closing the Loop Between System Timing and Signal Integrity Analysis"

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From: Todd Westerhoff (toddw@cadence.com)
Date: Thu Aug 17 2000 - 15:16:19 PDT


Hi everyone,

Cadence is sponsoring a free NetSeminar - basically an educational Web broadcast - on August 28th, at 10AM PST. This particular seminar targets the intersection of timing analysis and signal integrity, explaining how concepts such as buffer delay (remember Vmeas and Vref?) fit together with component timing characteristics to provide a more complete picture of system timing.

This seminar is intended as an introduction to the topic - so, while it goes into a lot of technical depth, it isn't intended to cover some of the more advanced issues that sometimes get discussed here. It's intended for those folks who are still uncertain about why and how the results of timing analysis and signal integrity analysis get put together.

This isn't intended to be a thinly veiled Cadence product pitch, or I wouldn't post it here.

For those of you who are interested in more detail, you can find a more detailed description of the seminar at:

http://www.netseminar.com/index.cgi?sem_num=308

... along with instructions for signing up, should you be interested in attending.

Comments on the seminar (should you choose to attend), and on this use of the Web as an educational vehicle are welcome and appreciated.

Private replies to me should be addressed to: toddw@cadence.com

Thanks,

Todd.

    Todd Westerhoff
    Product Marketing Director | High Speed Systems Design | Performance Engineering
    Cadence Design Systems | 270 Billerica Road | Chelmsford, MA 01824
    
    ph: (978) 262-6327
    fx: (978) 446-6798
    email: toddw@cadence.com
    internal information website: http://www-ma.cadence.com/~toddw

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