RE: [SI-LIST] : Decoupling capacitors (again!)

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From: Larry Smith (ldsmith@lisboa.eng.sun.com)
Date: Wed Aug 16 2000 - 15:55:52 PDT


Barry - The thin dielectric between pcb power planes has a number of
benefits. The most obvious is capacitance which is proportional to the
dielectric thickness. A little less obvious is the inductance which is
inversely proportional to thickness. The impedance of the power planes
is sqrt(L/C), so it is also inversely proportional dielectric
thickness. Your comment about sharing of decoupling capacitors is
directly related to impedance. With low impedance power planes, the
energy stored in all decoupling capacitors has a low impedance path to
get from the caps to the power-hungry chips that consume it.

One way of looking at this is that there is no point in putting a bunch
of low impedance capacitors on a board if we have not provided a low
impedance path to get the energy from the caps to the consumers. There
is no point in achieving a target impedance below 20 mOhms and above
100 MHz with capacitors unless our power plane path is less than 20
mOhms. It turns out that the spreading inductance of power planes
spaced 4 mils apart will give you roughly 20 mOhms at 100 MHz. We are
using Hadco 'buried capacitance' planes that are 2 mils apart in many
of our products to get lower impedance.

I don't have any references that give a quantitative treatment of
this. Istvan Novak and I are presenting papers at the EPEP conference
in Phoenix this October that discuss spice modeling of the power planes
(that is where my numbers come from) and the advantageous noise damping
properties that come with thin power plane dielectrics (assuming both
papers are accepted..). Istvan has already given the web site for the
NCMS group that is organizing a lot of this effort. I'll repeat it
here.

        http://edc.ncms.org/index.html
        
regards,
Larry Smith
Sun Microsystems

> Date: 16 Aug 2000 14:55:07 -0700
> X-Sent: 16 Aug 2000 21:55:07 GMT
> Content-Disposition: inline
> Mime-Version: 1.0
> To: Larry.Smith@eng.sun.com
> From: "Barry Ma" <barry_ma@altavista.com>
> Cc: si-list@silab.eng.sun.com
> Subject: RE: [SI-LIST] : Decoupling capacitors (again!)
> X-Sent-From: barry_ma@altavista.com
>
> Larry,
>
> Thanks a lot for your great note! It is very helpful.
>
> You mentioned small spacing between pwr and gnd planes in the PCB a couple of times in the
discussion. I'd like to add my 2 cents.
>
> In addition to enough capacitance between pwr and gnd planes for high frequencies noise to
go through, the small spacing also makes it possible for limited decoupling capacitors to be
shared by different gates. This is another important reason why much less numbers of decap
can practically work than calculated numbers.
>
> You suggested 5 mil or so spacing, Prof. Todd Hubing asked for at least < 10 mil. Is there
any articles giving quantitative description about the criteria?
>
>
>
> Thanks.
> Best Regards,
> Barry Ma <bma@anritsu.com>
> ANRITSU www.anritsu.com
> Morgan Hill, CA 95037
> Tel. 408-778-2000 x 4465
> _______________________________________________________________________
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