RE: [SI-LIST] : Decoupling capacitors (again!)

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From: Larry Miller (ldmiller@nortelnetworks.com)
Date: Tue Aug 15 2000 - 14:22:50 PDT


By definition these are pretty short, which is why you don't want to do the
series terminator thing.

Larry

> -----Original Message-----
> From: Vinu Arumugham [SMTP:vinu@cisco.com]
> Sent: Tuesday, August 15, 2000 12:33 PM
> To: Miller, Larry [SC7:322:EXCH]
> Cc: Zabinski, Patrick J.; si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Decoupling capacitors (again!)
>
> Please see comments below.
>
> Thanks,
> Vinu
>
> Larry Miller wrote:
>
>
>
> I think Pat's points are well-taken.
>
> Unless you are using ECL I think that you will find the situation
> self-limiting. For example, with BGAs it is not unusual to have on the
> order of 1 nH of inductance on the spreader board between the actual chip
> and the PCB (which brings up other problems, but never mind....)
>
> You certainly need to be thinking in terms of matched impedance PCB
> traces. I have had very good luck considering 100 MHz-ish parts to have 10
> to 30 ohms driving impedance (gotten from a least-squares fit to some IBIS
> data). This seems to hold up retty well over a number of vendors and
> geometries in the 0.25u range.
>
> Since most PCBs are set up with 50 ohm traces these days, that says
> you need source terminator resistors. This can also get out of hand, and I
> have had good luck making the PCB traces lower impedance. Unconventional,
> but try it with SPICE. You do end up with 10 to 15-mil wide traces, but in
> a tight layout thsi is OK if you have lots of layers.
>
>
> One thing to remember however, is that you could run into electromigration
> limits of the driving device by using lower impedance traces. Simulators
> usually do not flag such limits. To avoid reducing the part's life, it may
> be necessary to place tighter limits on the length/loading of such traces.
>
>
>
> Bear in mind that if you end up with calculated values that won't
> fit you have a situation where the chip vendors could not sell their
> wares! (See Pat's example below)
>
> My experience on this has been in the gigabit Ethernet area. (PHYs
> and MACs, switch fabrics and SDRAMs)
>
> I have found that if you
>
> 1) put a ring of 0603 caps outside a BGA ball pattern on the
> bottom side and
>
> 2) put another ring inside (between the BGA ball pattern for signals
> and the group of balls in the middle used for thermal grounding, if
> present), also on the bottom side
>
> 3) use a 50-50 mix of values of .01 uF and .001 uF, and
>
> 4) add a few bulk tantalums near the corners of the BGA
>
> you will be all right if
>
> 5) you have good ground and power planes in the center of the
> stackup with close spacing (.005" or so) between them.
>
> If it takes more than this, let's face it, you have a real
> problem....
>
> Larry Miller
>
> -----Original Message-----
> From: Zabinski, Patrick J. [SMTP:zabinski.patrick@mayo.edu]
> Sent: Tuesday, August 15, 2000 8:41 AM
> To: si-list@silab.eng.sun.com
> Subject: RE: [SI-LIST] : Decoupling capacitors (again!)
>
> Martin,
>
> I can't offer much advice, but I can possibly offer some
> comfort in that I've had the same problem. For one design
> I was recently involved in, I tried to follow the same
> approach/theory, and the end result was that I needed
> 80 decoupling capacitors per ASIC (to maintain 10%
> dV), and I had 32 ASICs per board (>2500 caps per board!).
> After having others verify
> my numbers/calculations, I took close look and realized
> the caps would consume more board space than the ASICs.
>
> I could not justify, believe, or afford this, so I
> ended up backing down and relying on my old rules of
> thumb (BTW: I hate rules of thumb, but I sometimes
> use them when I have no better way). The board works
> fine with only 12 caps per ASIC.
>
> Looking back, I can see three possible reasons why the
> approach you
> and I took is not quite complete:
>
> * component packaging effects are not taken to
> account. Not definite on this, but I believe
> a poor package would probably negate any capacitance
> you might have on the board.
> * the board's self-impedance. I believe Larry's
> approach addresses this as effective increase
> in inductance, but the ground/power plane itself
> does offer a low-impedance capacitance. Regardless
> if you have any discrete caps on or not, the planes
> offer some inherent, built-in capacitance.
> * most (all?) dI/dt effects are self-limiting.
> For the calculations you used, they assumed
> dV=0.0. However, if dV>0, then dI/dt will
> be reduced all on its own. I don't have any
> data or theories on how much, but dI/dt
> is likely to be reduced from what you
> predicted (also tied into/related to the
> first issue about packaging).
>
> Sound reasonable? Comments?
>
> Anyway, I sympathize and hope you find a solution. If you
> do, please share.
>
> Pat
>
> > -----Original Message-----
> > From: Martin J Thompson [ <mailto:Martin.J.Thompson@trw.com>]
> > Sent: Tuesday, August 15, 2000 9:49 AM
> > To: <"si-list@silab.eng.sun.com"
> > Subject: [SI-LIST] : Decoupling capacitors (again!)
> >
> >
> > Hi all, this is my first time posting here, although I've
> > been lurking for a while.
> >
> > My problem is figuring out the decoupling requirements for
> > this system:
> > FPGA, DSP, 6 SDRAMS, 2 flash, DPRAM, clock frequency is 100MHz.
> >
> > According to my calculations, my I/O's need to drive a total
> > of about 1.5nF of I/O and trace capacitance.
> > To achieve the 0.5ns edges that the FPGA will drive (3.3V
> > supply) it looks like I need dI=4amps. This is assuming that
> > 50% (is this typical?) of the I/O's toggle each cycle.
> (dI=0.5Cdv/dt)
> >
> > To achieve a dV of < 0.1V this implies a target impedance of
> > around 20mohm, flat up to 1GHz! (Z=dv/di)
> >
> > This then seems to need around 500-800 decouping caps spread
> > around, which is an order of magnitude more than I've ever
> > used in the past. This is the first time I have taken a
> > 'design' approach to the problem, but the previous boards
> > have worked, using various rules of thumb.
> >
> > Is this sort of number of caps to be expected in this sort of
> > system, or can anyone see any sillies in my understanding (or
> > even in the sums!)?
> >
> > Now, if I don't get right out to 1GHz, the edges will suffer,
> > but that wouldn't necessarily matter if they stayed below
> > 1-1.5ns. Or would this cause the supply to droop elsewhere?
> >
> > As you might gather from the analysis above I've read Larry
> > Smith and co's paper on decoupling design, which states that
> > a flat target impedance is indicated. If I can analyse my
> > application enough, can I then shape the Ztarget vs frequency
> > to make life easier?
> >
> > Many thanks for your time, any help greatly appreciated,
> >
> > Martin
> >
> >
> >
> > TRW Automotive Advanced Product Development,
> > Stratford Road, Solihull, B90 4GW. UK
> > Tel: +44 (0)121-627-3569
> > <mailto:martin.j.thompson@trw.com>
> >
> >
> >
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