**From:** Greim, Michael (*[email protected]*)

**Date:** Fri Aug 11 2000 - 10:58:10 PDT

**Next message:**Hassan Ali: "RE: [SI-LIST] : Tools for high-speed interconnect design"**Previous message:**Charles Grasso: "Re: [SI-LIST] : Tools for high-speed interconnect design"**Maybe in reply to:**David Haedge: "[SI-LIST] : LVDS Skew"**Next in thread:**S. Weir: "RE: [SI-LIST] : LVDS Skew"**Reply:**S. Weir: "RE: [SI-LIST] : LVDS Skew"

With a rise time of 400 pS the differential switching

resembles an X. Move either waveform by 200 pS and

your differential switch point resembles /\ or \/.

I hope this helps your visualization.

MG

-----Original Message-----

From: Ricchiuti Vittorio [mailto:[email protected]]

Sent: Friday, August 11, 2000 3:56 AM

To: Scott McMorrow; [email protected]

Subject: RE: [SI-LIST] : LVDS Skew

Scott,

I don't understand why the differential crossing ceases to exist when the

skew between signals is 200ps. Why not 400ps?

Regards

Vittorio

ing. Vittorio Ricchiuti

CAD support and SI engineer

Siemens ICN

Loc. Boschetto

67100-L'Aquila

ITALY

-----Original Message-----

From: Scott McMorrow [mailto:[email protected]]

Sent: Thursday, August 10, 2000 1:50 AM

To: Vinu Arumugham; [email protected]

Subject: Re: [SI-LIST] : LVDS Skew

Vinu,

Take two sides of a differential transition that goes from

low to high in 400ps with a perfectly balanced transition.

Call the differential crossing point 0ns. Thus the complete

differential transition (irrespective of the bit rate) occurs

in +/-200 ps.

Now skew one side of the pair thus translating one of the

waveforms. As the skew increases, the differential crossing

point slides up (or down, depending on the edge) in voltage.

Eventually, in this case at 200 ps of skew, in a noiseless

perfect system the differential crossing ceases to exist.

This is true no matter what the bit period is and is dependent

only on the edge transition time of the differential signals. You

can prove this to yourself by taking two pieces of paper.

On one draw a rising edge. On the other draw a falling edge.

both should have the same edge transition time and same

low to high signaling level.

Now, assuming you can see through the paper, align the

edges so that they cross exactly in the center. Then, slide

the falling edge to the right. The crossing point moves up

in voltage and out in time across the rising edge. This is

what differential skew does to the signal seen at the

receiver.

After 1/2 the edge transition time the crossing point is at

the high signaling level, where a differential crossing no

longer exists.

Now increase the edge transition times by a factor

of 2:1. There is now twice as much latitude for differential

skew.

The moral of this story is to use the slowest edge rate necessary

to sustain a particular operating bit period. It is more tolerant of

differential skew.

regards,

scott

-- Scott McMorrow Principal Engineer SiQual, Signal Quality Engineering 18735 SW Boones Ferry Road Tualatin, OR 97062-3090 (503) 885-1231 http://www.siqual.comVinu Arumugham wrote:

> Scott McMorrow wrote: > > > David, > > > > It depends on the edge rate of LVDS signal. Differential skew, besides > > causing common mode currents, will cause a translation in time and voltage > > of the differential crossing point. This causes the received Eye to close > > down and may be perceived as timing jitter. If the skew is greater than > > 50% of the edge transition time, then the eye becomes totally closed. > > (i.e. A 50% edge transition time skew causes the differential crossing to > > never be seen at the receiver.) > > > > This may be true if the period = 2 x transition time. But at 200MHz, this > does not look like a possibility. > > > > > Some LVDS drivers have edge rates in the 400ps range. 200ps of skew > > would totally close the eye. 50ps of skew would reduce the eye opening > > by 25%, a significant reduction in noise margin. > > > > With 1ns edge rate drivers, like some of the "nice" LVDS devices, 50ps > > of skew is not a big deal. This translates to only a 10% noise margin > > reduction. > > > > regards, > > > > scott > > > > -- > > Scott McMorrow > > Principal Engineer > > SiQual, Signal Quality Engineering > > 18735 SW Boones Ferry Road > > Tualatin, OR 97062-3090 > > (503) 885-1231 > > http://www.siqual.com > > > > David Haedge wrote: > > > > > Dear SIer's: > > > > > > I have a person concerned about 55ps of skew between the two traces > > > on an LVDS differential pair. The LVDS bus is running at 200MHz, a > > > 5ns period. What negative effect on the system would occur if say, > > > there was a 100ps or even 200ps mismatch? Timing margins are > > > still within spec with even a 1ns mismatch. Some common mode > > > currents may be launched, but I think they would cause minimal > > > noise and not cause any circuit upsets. Has anybody seen problems > > > with LVDS signaling with >55ps diff pair line skew? > > > > > > David Haedge > > > Raytheon > > > > > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > > > [email protected] In the BODY of message put: UNSUBSCRIBE > > > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > > > si-list archives are accessible at http://www.qsl.net/wb6tpu > > > **** > > > > **** To unsubscribe from si-list or si-list-digest: send e-mail to > > [email protected] In the BODY of message put: UNSUBSCRIBE > > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. > > si-list archives are accessible at http://www.qsl.net/wb6tpu > > ****

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**Next message:**Hassan Ali: "RE: [SI-LIST] : Tools for high-speed interconnect design"**Previous message:**Charles Grasso: "Re: [SI-LIST] : Tools for high-speed interconnect design"**Maybe in reply to:**David Haedge: "[SI-LIST] : LVDS Skew"**Next in thread:**S. Weir: "RE: [SI-LIST] : LVDS Skew"**Reply:**S. Weir: "RE: [SI-LIST] : LVDS Skew"

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