Re: [SI-LIST] : RE : LVDS Skew

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From: Scott McMorrow (scott@vasthorizons.com)
Date: Thu Aug 10 2000 - 13:49:12 PDT


MikonCons@aol.com wrote:

>
> As I see it, there is no direct eye pattern correlation in system
> functionality (or malfunction) except on differential clock lines or in chips
> operating at (or above) the clock frequency. Perhaps someone can cite
> exceptions to this (perhaps ignorant) view.
>
>

Yes, to differential clock lines I would also add self-clocked (clock-encoded)
circuits.

LVDS interfaces generally use a seperate differential clock for an
entire group of data circuits. There are certainly other differential interfaces
where the clock is encoded in and recovered from the data stream. In these
cases, each differential pair must be treated like a differential clock and have
enough skew control to keep the differential switch point well away from
the high and low signalling levels where noise can cause some terribly nasty
glitches to occur in receivers.

The data(only) differential pairs would not have to be skew controlled
when timing constraints are not a concern. Skew is a concern with clock and
clock encoded signals. With both edge clocking, it can cause some excessively
high jitter at the clock recovery circuit, too.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

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