RE: [SI-LIST] : Effects of thieving on SI and EMC.....

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From: Ken Willis (Ken.Willis@siroccosystems.com)
Date: Wed Aug 09 2000 - 04:40:17 PDT


This one took me back a bit to my first job out of school, which
was as a process engineer at a PCB fab shop. The reason for the
thieving is to enhance plating uniformity. Boards electroplate
from the outside in, so on a big board, you will get more copper
deposited around the outer features of the board than in the middle.
The thieving is generally meant to take the brunt of this, and let
you plate the features you care about a bit more evenly.
On a big , thick board, it is tough to get a mil of copper plated
in small vias in the middle of the board. The thieving helps to
balance this out a bit.

The HASL process is seperate from the plating process. It goes like
this in general:

        - print and etch the inner layers
        - laminate them together
        - drill the vias
        - electroless plate the bare copper boards, just to get
          the vias to conduct
        - print the image on the external layers
        - electroplate copper to create the external
          features and plate up the vias
        - electroplate solder on top of that
        - strip off the plating photoresist
        - etch the external layers (the solder acts as the etch resist)
        - strip off the solder
        - apply solder mask

Now you have the basically finished PCB, with exposed copper for the
surface mount pads. The external copper traces are all buried under the
solder mask. Now the boards are run through HASL, to cover all the exposed
copper with a layer of solder. That's about it.

For copper thickness, if you start with 1/2 oz. copper (about 0.7 mils)
externally, and plate a mil in the vias, you will end up plating up the
external traces about 1oz, and finish at about 2.1 mil thick traces.
Also, for any high speed signals, pin escape and get down to internal
layers immediately. Besides for EMI reasons, the external etch is much
less controllable than internal layers due to plating distribution. It is
very tough to have impedance control on external layers. The best the
supplier
can do generally is to get the impedance coupons to come out, but who knows
what the variation over the board will be. I've seen a wide range.

Ken Willis
Sirocco Systems
        

-----Original Message-----
From: Dan Irish - Sun BOS Hardware [mailto:Dan.Irish@east.sun.com]
Sent: Tuesday, August 08, 2000 6:09 PM
To: si-list@silab.eng.sun.com
Cc: Dan.Irish@east.sun.com
Subject: RE: [SI-LIST] : Effects of thieving on SI and EMC.....

Ray, all,

From what I understand, many PCB fab suppliers use
HASL (Hot-Air Solder Levelling) to plate the top and bottom
layers (from 1/2 oz copper to 1 oz, typically.)
HASL depends on uniform PCB thickness to work well.
To achieve uniform thickness, grids of small copper filled square
or circular "thieving pads" are added to layers that would
otherwise have large areas free of copper signals or plane shapes.
"Thieving pads" prevent too much copper from being thieved-away
during etching.

From an EMI standpoint, I believe the effect of thieving pads
depends on the grounding philosophy--whether chassis ground
is isolated from logic return as advocated by Henry Ott
or whether multi-point or hybrid grounding is used.

I have separated chassis ground from logic return with occasional
single-point grounds very successfully (again per Ott,) and thieving pads
have been a big EMI problem for me several times.
You could say this is a pet peeve of mine.

Here's a example--for a typical I/O board layout, chassis ground
is provided from the I/O sheet metal to the connector shields
to a chassis ground shape on the PCB that surrounds the I/O connectors.
All power and logic return (GND) planes and non-I/O signals
are cut back away from the I/O area, leaving a gap where only
EMI filter components are placed and I/O signals are routed.
I use 100 mils minimum spacing (rule-of-thumb by Stan Woo)
to prevent capacitive coupling of RF noise from the inside
to the quiet chassis ground.

Thieving pads are then added by the PCB supplier, which can
make very good stepping stones for capacitive coupling across
this gap. To prevent this, I specify a thieving pad keep-out
area in this gap on the fab drawing.

Regards,
Dan

> From: "Greim, Michael" <mgreim@mc.com>
> To: "'Ray Anderson'" <raymonda@radium.eng.sun.com>, "Greim, Michael"
<mgreim@mc.com>
> Cc: SI LIST <si-list@silab.eng.sun.com>
> Subject: RE: [SI-LIST] : Effects of thieving on SI and EMC.....
> Date: Tue, 8 Aug 2000 14:45:55 -0400
> MIME-Version: 1.0
>
> A thieving pattern is a bunch of very small shapes
> added to a layer that helps equalize the plating
> across a given layer (increases manufacturability).
> An auto thieving utility or program uses a set of
> criteria to determine how and where to put these
> shapes. Unfortunately these programs are almost
> exclusively focussed on mfg issues and not SI or
> EMC issues.
>
> Usually if you see a bunch of 1/16" width diamonds
> on an artwork layer, this is thieving.
>
> FYI
>
> MG
>
> -----Original Message-----
> From: Ray Anderson [mailto:raymonda@radium.eng.sun.com]
> Sent: Monday, July 31, 2000 11:12 AM
> To: Greim, Michael
> Cc: SI LIST
> Subject: Re: [SI-LIST] : Effects of thieving on SI and EMC.....
>
>
> OK, I'll bite. Educate me, what is a thieving pattern,
> and an auto-thiever ????
>
>
> -Ray
>
>
> > Does anyone out there have a tool or reference
> > that would allow one to calculate the effects of
> > thieving patterns on signal integrity and EMC.
> >
> > I am trying to come up with appropriate rule sets
> > for driving an auto-thiever utility.
> >
> > Thanks for the help.
> >
> > MG
> >
>
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