**From:** Peterson, James F (FL51) (*james.f.peterson@honeywell.com*)

**Date:** Tue Aug 08 2000 - 10:03:41 PDT

**Next message:**Greim, Michael: "[SI-LIST] : Effects of thieving on SI and EMC....."**Previous message:**Patrick Riffault: "Re: [SI-LIST] : Bus Design Methodology in SpectraQuest"**Maybe in reply to:**Cosmin Iorga: "[SI-LIST] : Via model"

(Sorry if this gets sent twice, but it looks to me like it was lost in the

ether)

Speaking as a user of SI tools, I agree that there seems to be a hole in our

approach. Most tools that I've seen assume perfect reference planes. They

first assume that each plane is a perfect plane without any holes or

discontinuities in it. They secondly assume that the power plane is a

perfect ac equivalent of the ground plane. Maybe it would be too taxing

time-wise for these tools to assume otherwise during the signal integrity

routing and analysis of critical nets (I haven't looked at Sigrity's tool).

But it would be nice if we had a tool that could ALSO look at our decoupling

to verify the ac equivalence between pwr and gnd planes. And it would be

nice if we had a tool that could ALSO look at that hunk of swiss cheese we

call a reference plane and verify it still works the way we think it's going

to work.

Jim Peterson

james.f.peterson@honeywell.com

Honeywell, Space Systems Division, M/S 934-5

13350 US 19 N., Clearwater, FL, 33764-7290

Office : 727-539-2719

FAX : 727-539-2183

-----Original Message-----

From: Raymond Y. Chen [mailto:chen@sigrity.com]

Sent: Friday, August 04, 2000 2:00 PM

To: Todd Westerhoff; si-list@silab.eng.sun.com

Cc: iorgac@std.teradyne.com

Subject: RE: [SI-LIST] : Via model

Todd,

I agree with you on most of the things that you pointed out in your email.

But there is one thing that either you don't know about it or you don't want

to mention it, which is: there is a commercial tool that can effectively and

promptly solve very-complex packaging structures involving power delivery

system and signal delivery system, and the interactions between them, hence,

the return path.

You are right, modeling multi-layer power/ground plane structures with tens

of thousands of power/ground vias is a very challenging job because of its

distributive-circuit nature. That is why the traditional 2-step approach on

power/ground modeling is not realistic on real world problems.

Step 1, use EM field solvers to extract a circuit network to represent the

power delivery system;

Step 2, then combine the power/ground model with the driver/receiver into a

SPICE stack, and ask SPICE type of circuit solve to do the simulation.

As you know, even if the EM extraction can handle the complexity, the

extraction itself takes 0 second, and the extracted circuit model is

accurate enough to represent all the wave-propagation phenomena inside the

multi-layer structure, we still can not finish step 2 due to the size of the

circuit matrix need to be inversed.

So is there a good approach to model/simulate the power/ground return path,

as you wondered? I believe, technically, there is a very good way to do

that - a hybrid methodology that uses EM field solver to calculate the EM

fields inside the packaging structure, while uses circuit solvers to compute

the voltages and currents in the non-linear/linear circuit components, and

the field solver and circuit solvers are linked together and run

simultaneously, hence changing the traditional 2-step approach to a 1-step

solution.

What is the benefit of this approach on power/ground/signal integrity

analysis? Check out the demo of our software tool SPEED97 at,

http://www.sigrity.com/download/demo/spd_demo.exe, the very first example

provided in the user's manual, is the exact structure that Cosmin asked XTK

and SPECCTRAQuest to solve. You will find, Todd, the simulation time of our

tool in this case is only a few second (not hours). And you can also see the

animated waveform of power/ground noise propagation, return path

discontinuity, and signal transmission, while the simulation is running.

BTW, the SPEED2000 demo version will be available for download in 2-weeks.

Raymond Y. Chen

Vice President, Products and Services

*-------------------------------------------------------

* Sigrity, Inc. Tel: 408.377.2180

* 2105 Hamilton Ave. Suite 310 Fax: 408.377.2565

* Santa Clara, CA 95125 Web: www.sigrity.com

*-------------------------------------------------------

*>-----Original Message-----
*

*>From: owner-si-list@silab.eng.sun.com
*

*>[mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Todd Westerhoff
*

*>Sent: Friday, August 04, 2000 9:02 AM
*

*>To: si-list@silab.eng.sun.com
*

*>Cc: iorgac@std.teradyne.com
*

*>Subject: Re: [SI-LIST] : Via model
*

*>
*

*>
*

*>Cosmin,
*

*>
*

*>You've got a good question, and a valid concern, but the answer is
*

*>long and involved. Let me see if I can give the short answer coherently.
*

*>
*

*>The return path - the thing you're ultimately concerned about - is
*

*>a function of a lot more than just the via model. As a matter of
*

*>fact. although the via model certainly has something to do with
*

*>it, the real issue is the presence or absence of high-frequency
*

*>decoupling between the signal's reference planes in the vicinity
*

*>of the via. The via model itself could not predict this, and
*

*>thus, wouldn't give you what you're after.
*

*>
*

*>Analyzing return paths in the time domain requires a tool that
*

*>properly models the power supply, decoupling capacitors and power
*

*>planes, in addition to the trace being studied. That requires
*

*>that the planes be modeled as a mesh with their associated
*

*>non-ideal characteristics, such that the localized effects of
*

*>power demand (i.e. switching current), decoupling and the
*

*>transition of a signal between reference planes can be
*

*>analytically predicted.
*

*>
*

*>That also means that the modeling / analysis time would jump from
*

*>seconds/minutes to hours/days, depending on the complexity of the
*

*>model. As far as I know, there are no current commercial
*

*>analytical solutions to the problem you propose - and that's not
*

*>for lack of desire. It's because of the complexity of the problem.
*

*>
*

*>The biggest question - and the biggest challenge - with simulation
*

*>tools is understanding the limits of their accuracy, and in that
*

*>light, the correct way to apply them to a problem, and the
*

*>conclusions that can/cannot be drawn from the results. Most
*

*>commercial SI tools make the assumption that reference planes
*

*>behave ideally, and that trace behavior can be predicted from the
*

*>2-D cross-sectional characteristics of the trace and its distance
*

*>from its respective reference planes. That assumption, and a few
*

*>others, makes it possible to simplify the modeling problem to the
*

*>point where circuit extraction and simulation can take place as an
*

*>interactive process - point to a trace, and get a result.
*

*>
*

*>If you want to get a more accurate answer, you can, but the cost
*

*>is a substantial increase in the complexity of the circuit
*

*>extraction, modeling and analysis processes. Ask anyone who's
*

*>using a 3-D field solver in conjunction with SPICE what their
*

*>process is, and how long it takes to generate a model and run
*

*>analyses. It ain't seconds, and it ain't minutes.
*

*>
*

*>So - the real question is - which approach do you use, and when?
*

*>I would argue that you're best off using the interactive tools to
*

*>study the problem and hone-in on a potential solution to a
*

*>problem, keeping in mind the limitations of the tools, their
*

*>applicability to the problem at hand, and the likely amount of
*

*>error you expect in the analysis. Once you're close, you can use
*

*>a more detailed, and lengthy analysis process to close in on the
*

*>ultimate answer, should you need to do so.
*

*>
*

*>In the particular case of return path analysis, I'm not sure that
*

*>you'll find any commercial that satisfy your need. The
*

*>alternative is to use an expert-based rules system to examine the
*

*>design, checking against a known set of design rules. This isn't
*

*>an analytical approach, but it serves to automatically and
*

*>highlight areas that deserve thought (and possibly) detailed
*

*>analysis using some other method. A common example is the case
*

*>where a trace runs across a split plane with no localized
*

*>decoupling (between the planes). The additional loop inductance
*

*>caused by the discontinuity in the return path degrades the
*

*>signal's edges and frequently causes the circuit to fail. The
*

*>case you propose is similar - the transition between layers
*

*>changes the signal's reference plane, and will have the same
*

*>effect - increasing the loop inductance. There are commercial
*

*>tools available that deliver the expert-based rules checking
*

*>capability, which (at least) provide a fast way to highlight
*

*>problem areas, even if they don't analytically predict the effect
*

*>on the circuit.
*

*>
*

*> Anyway, that's my $0.02. Hope you found it useful.
*

*>
*

*>Todd.
*

*>
*

*>
*

*>
*

*>
*

*>
*

*>
*

*>At 10:02 AM 8/3/2000 -0700, Cosmin Iorga wrote:
*

*>>Does anybody know a field solver that can extract and simulate
*

*>>a via model from a board database? The via model should include
*

*>>both signal and return path if the transmission line changes the
*

*>>reference plane. The following picture tries to illustrate it:
*

*>>
*

*>>
*

*>>
*

*>> ______________________________
*

*>>|______________________________| <-- trace 1 (top layer)
*

*>> ||
*

*>> ___________________________ || __________________________________
*

*>>|___________________________ || ________________ground plane 1____|
*

*>> || ||
*

*>> signal via --> || || <-- ground via (return path)
*

*>> || ||
*

*>> ___________________________ || ___||_____________________________
*

*>>|___________________________ || ________________ground plane 2____|
*

*>> ||
*

*>> _||________________________________
*

*>> trace 2 (bottom layer)--> |___________________________________|
*

*>>
*

*>>
*

*>> The signal propagates through trace 1, which is a microstrip
*

*>> line referenced to ground plane 1, then through the via and
*

*>> trace 2, which is a microstrip line referenced to ground plane 2.
*

*>> The return path for the current consists of ground plane 2,
*

*>> ground via, and ground plane 1. The transition from the top
*

*>> to the bottom layer will look more inductive if the distance
*

*>> between the signal and ground vias increases. So far I've tried
*

*>> XTK and SPECCTRAQuest but none of them could extract correctly
*

*>> this via model.
*

*>>
*

*>>
*

*>> Best Regards,
*

*>>
*

*>> Cosmin Iorga
*

*>> (818) 874-7149
*

*>>
*

*>>
*

*>>
*

*>>**** To unsubscribe from si-list or si-list-digest: send e-mail to
*

*>>majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
*

*>>si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
*

*>>si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*>>****
*

*>
*

*>
*

*> Todd Westerhoff
*

*> Product Marketing Director | High Speed Systems Design |
*

*>Performance Engineering
*

*> Cadence Design Systems | 270 Billerica Road | Chelmsford, MA 01824
*

*>
*

*> ph: (978) 262-6327
*

*> fx: (978) 446-6798
*

*> email: toddw@cadence.com
*

*> internal information website: http://www-ma.cadence.com/~toddw
*

*>
*

*>**** To unsubscribe from si-list or si-list-digest: send e-mail to
*

*>majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
*

*>si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
*

*>si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*>****
*

*>
*

**** To unsubscribe from si-list or si-list-digest: send e-mail to

majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE

si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.

si-list archives are accessible at http://www.qsl.net/wb6tpu

****

**** To unsubscribe from si-list or si-list-digest: send e-mail to

majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE

si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.

si-list archives are accessible at http://www.qsl.net/wb6tpu

****

**Next message:**Greim, Michael: "[SI-LIST] : Effects of thieving on SI and EMC....."**Previous message:**Patrick Riffault: "Re: [SI-LIST] : Bus Design Methodology in SpectraQuest"**Maybe in reply to:**Cosmin Iorga: "[SI-LIST] : Via model"

*
This archive was generated by hypermail 2b29
: Wed Nov 22 2000 - 10:50:58 PST
*