From: Matthias Mansfeld ([email protected])
Date: Tue Aug 01 2000 - 13:57:08 PDT
I would like to read some opinions about a rather dense design
(double side populated) with some high speed issues. Please apologize
my beginner's questions, but this is my first design with controlled
impedance differential pairs.
Maybe somebody can recommend an optimal layer stackup for this
Planned is 6 Layer, FR4, end thickness 1.5 mm (cost reasons)
There are mostly "non-critical", more short or slow digital signals
but about 10 high speed differential signals with 100 Ohm
my first (and most preferred) idea is the following stack-up
- best power decoupling with adjacent power layers
- maybe higher emission level, because no "shielding"
- impedance lines must be routed on inner layers sig2 or sig3 (maybe
this is more advantage than disadvantage - on outer layers there
will be not much space - full of fine pitch stuff....)
How can I calculate this "embedded differential strip lines" on
sig 2 or sig3? Any good recommendations for the best geometry (line
width, distance, FR4 thicknesses)? How is the impact of any
structures on the outer layers?
- better shielding from signals on sig2,3
- worse power/gnd decoupling
- impedance controlled lines on all signal layers possible (but not
much space on sig1 and sig4) Same questions as above....
Which stackup is better?
Many thanks for any ideas and hints...
Matthias Mansfeld Elektronik
* Printed Circuit Board Design and Assembly
Am Langhoelzl 11, D-85540 Haar, GERMANY
Phone: +49-89-4620 0937, Fax: +49-89-4620 0938
E-Mail: [email protected]
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