RE: [SI-LIST] : Parallel Termination in Theory and Practice

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From: Gaboian, Jerry (j-gaboian@ti.com)
Date: Mon Jul 24 2000 - 05:10:13 PDT


Abe,

If you calculated the critical length for the stub in each case and divided
it by six as Howard recommends, would there be any differences in the
capacitive loading?

Thanks,
Jerry Gaboian

-----Original Message-----
From: abe riazi [mailto:ariazi@serverworks.com]
Sent: Saturday, July 22, 2000 1:18 AM
To: 'si-list@silab.eng.sun.com'
Subject: [SI-LIST] : Parallel Termination in Theory and Practice

Dear Scholars:

Included on Page 230 of "High-Speed Digital Design A Handbook of Black
Magic" by H.W. Johnson and M. Graham, is Figure 6.7 intended to illustrate
the "Right" and "Wrong" ways of applying parallel termination.

This idea is reflected by the attached gif picture. The two inserted marks
!? imply it is theoretically valid but may not hold true in practice; as
explained by the following paragraphs.

In theory, the optimum location for a parallel end terminator is beyond the
chip shown by Figure A, as placing the terminator before the chip ( Figure
B) is accompanied by undesirable capacitive loading effects of the stub
separating the two components. Indeed, several important features of
parallel termination (for instance its advantages over series termination
which include allowing distributed load, undistorted waveform along full
trace path and faster circuit performance)are optimally revealed when the
terminator is located beyond the receiver as exemplified by Johnson and
Graham. This theoretical superiority for placement of parallel
terminators can be also easily verified via simulation. A useful reminder
when simulating parallel or series termination; in the so called FF corner
(i.e. Fast buffer and Fast environment) the largest value of the parallel
and the smallest value of the series terminators (as dictated by each
resistor's nominal value and tolerance) should be used. The opposite
applies to the SS (Slow buffer, Slow environment ) simulation corner.
Another noteworthy consideration for parallel termination is selection of
one or two resistors schemes. Using one resistor often proves more
economical in terms of cost, PCB space and power consumption; though, there
are instances when use of two resistors (or Thevenin) is preferable. In
parallel terminations involving one resistor the optimum termination voltage
is often neither GND nor Vdd; instead an intermediate voltage Vtt = Vdd/2
which can require additional voltage source (regulator). Consequently, when
only few signal lines need termination it can be advantageous to use two
resistors (connected to GND and Vdd) rather than one demanding an extra
regulator.

In practice, there are cases in which placement of the parallel termination
past the receiver is not achievable. Placing the terminator before the chip
requires only one time routing to the receiver, whereas positioning the
resistor beyond the IC can impose routing under the chip twice (once from
the driver to the receiver, and then from the receiver pin to termination).
Therefore, for a receiver chip with a large number of pins (for example, BGA
with more than 500 pins) the latter approach can prove impractical due to
routing complexities.

In closing, Figure 6.7 of "High-Speed Digital Design A Handbook of Black
Magic" indicates that the best location for a parallel terminator is beyond
the last receiver IC (in a chain). This is valid in theory and verifiable
by means of simulation. However, it has important practical limitations as
placing the resistor past the chip requires routing twice, whereas
positioning the terminator before the IC is achievable with only one time
routing to the receiver pin.

Your comments are appreciated.

Respectfully,

Abe Riazi
Serverworks
2251 Lawson Lane
Santa Clara, CA 95054

 

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