From: Sandy Taylor (firstname.lastname@example.org)
Date: Thu Jul 20 2000 - 14:01:30 PDT
> Sandy, all,
> Any decoupling on IO sections?
This chip used slew rate and impedance controled drivers to
minimize the L dI/dT effects. The problem is much less severe than
in the core. There were passive decoupling caps in the IO,
but not the actively switched devices as in the core.
There is a paper on the dynamic termination output driver
in ISSCC 2000. The output/termination current vs voltage
looks almost like a 50 ohm resistor over process voltage
> email@example.com wrote:
> > David Chengson wrote:
> > > Does anyone have some approximate numbers for
> > > the amount of on-chip capacitance that has been explicitly
> > > added to large commercial or non-commercial chips?
> > ...
> > David
> > I co-authored a paper at Sun Microsystems which was presented
> > ISSCC 2000 describing the passive on chip decoupling caps
> > and the active circuit used to counter multi cycle effects.
> > Here are the numbers from that paper:
> > Passive capacitance added: 176 nF
> > Intrinsic chip capacitance: > 80 nF
> > On chip regulator capacitance: 134 nF (when deactivated)
> > regulator capacitance (switching): 1.6uF
> > This was for a 1.5V 0.15u CMOS device.
> > The on chip regulator uses actively switched decoupling capacitors to
> > decrease the AC impedance in a band limited range.
> > The target band was to cover the region between where the on chip passive
> > decoupling caps run out of gas and when the package(...) inductance
> > finally allows the current to change.
> > Keeping the on chip power supply impedance down in the
> > single digit mOhms is tough.
> > I hope this helps you.
> > Taylor
> > (360) 376 3815
> > CMOS Solutions
> > Orcas Island WA.
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