RE: [SI-LIST] : inductance extracted by ansoft SI3D

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From: Chris Cheng (chris.cheng@3pardata.com)
Date: Mon Jul 17 2000 - 21:46:30 PDT


even more interesting.
if you are dealing with 2.5gb/s, i am assuming you
are using differential signals which means you will
probably need odd mode parasitics. that will be an
interesting measure for any tdr to do.
the real question is how are you going to maintain
a 100ps edge through a package before it even hit the
pcb.
chris

-----Original Message-----
From: Doug McKean [mailto:dmckean@corp.auspex.com]
Sent: Monday, July 17, 2000 4:25 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : inductance extracted by ansoft SI3D

Very good questions Hassan.

100ps edges gives you about a 3 to 5 GHz bandwidth
and a critical length for the trace running at about
3 GHz of about 1/4". I can see your concern now with
a 0.235" length via.

My solution? Drop a grounded via down next to your
signal via to maintain a vertical ground reference,
fudge around with some geometric parameters so as to
maintain your impedance as best you can, and run
with it.

As far as the simulation of grounds and vias, where
do you stop? That can become an art form. You're
going to have to talk with some of the real gurus.

Try starting with ...

 http://www.qsl.net/wb6tpu/si-list2/pre99/0766.html
 http://www.qsl.net/wb6tpu/si-list2/pre99/0768.html

- Doug

> Hassan Ali wrote:
>
> Doug,
>
> That was a simplified sketch of via on a 24-layer pcb, 0.235" thick
> and has to operate at 2.5GB/s, 100ps risetime. Probably that
> equivalent circuit was an overkill, but how do I know that, and what
> would a simplified version be?
>
> Thanks.
>
> Hassan.

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