From: Chris Cheng ([email protected])
Date: Mon Jul 17 2000 - 13:55:33 PDT
i don't know anything about si3d. but here are ways to get via parasitics.
roger harrington (of bem/mom fame) used to defined excess inductance and
delta of inductance/capacitance w & w/o the parasitic. if u believe u have
simulator, built a 3d structure of the via with signal leads. then build the
the leads only without the via. subtract the inductance/capacitance between
the two results
and you've got a lump approximation of the parasitic. the original
methodology use a more
elegant technique to only solve for the delta fields to minimize the error
due to trying to
get a small delta out of two larger number.
anyone who claims to be able to tdr a single via and get meaningful result
however, lump parameters can be calculated by following techniques
(i) build two structures, one with a single trace the other with a match
but with lots > 50 vias uniformly placed on it. use a low speed capacitance
measure the low speed capacitance of each structure and subtract the
divide by the # of via.
(ii) once you figure out the lump capacitance, build two structures, one
with single trace
the other with daisy chained vias and match length. tdr the impedance and
use the formula
Z = sqrt( (l+ delta l)/(c+delta c)) to figure out the lump inductance.
and if u have done the above, you will find out those numbers are very small
models works fine. anyone who thinks u need hfss or whatever full wave
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