RE: [SI-LIST] : on-chip capacitance & core noise

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From: Zabinski, Patrick J. (zabinski.patrick@mayo.edu)
Date: Mon Jul 17 2000 - 12:54:12 PDT


David,

For references on how much other folks have added, check out:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
TITLE Circuit Design Techniques for the High-Performance CMOS IBM S/390
Parallel Enterprise Server G4 Microprocessor
AUTHOR L. Sigal, J. D. Warnock, B. W. Curran, Y. H. Chan, P. J. Cmporese,
M. D
. Mayo, W. V. Huott, D. R. Knebel, C. T. Chuang, J. P. Eckhardt, and P. T.
Wu
SOURCE IBM J. Research and Development
DATE 1997, Volume 41, Number 4/5
KEYWORDS processor, chip, design, decoupling
PAGES na
@@@@
In "Technology Features and Chip Characteristics" section, the
authors describe the inclusion of 102 nF of thin-oxide on-chip
decouping capacitance and nearly the same amount of well-capacitance.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
TITLE MCM Technology and Design for teh S/390 G5 System
AUTHOR G. A. Katopis, W. D. Becker, T. R. Mazzawy, H. H. Smith, C. K.
Vakirtzi
s, S. A. Kuppinger, B. Singh, P. C. Lin, J. Bartells, Jr., G. V. Kihimire,
P. N
. Venkatachalam, H. I. Stoller, J. L. Frankel
SOURCE IBM J. Research and Development
DATE September/November 1999, Volume 43, Number 5/6
PAGES 621-650
KEYWORDS MCM, processor, chip, design
@@@@
On page 635, the paper uses a formula that requires 8X added on-chip
decoupling capcaitance beyond the switched capacitance. The authors
give no reference to where "8X" came from.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
TITLE Chip Integration Methodology for the IBM S/3990 G5 and G6 Custom
Micropr
ocessors
AUTHOR R. M. Averill III, K. G. Barkley, M. A. Bowen, P. J. Caporese, A. H.
Da
nky, R.F.Hatch, D. E. Hoffman, M. D. Mayo, S. A. McCabe, T. G. McNamara, T.
J.
McPherson, G. A. Northrop, L. Sigal, H. H. Smith, D. A. Webber, and P. M.
Willi
ams
SOURCE IBM J. Research and Development
DATE September/November 1999, Volume 43, Number 5/6
PAGES 681-706
KEYWORDS MCM, processor, chip, design
@@@@
On pages 684-685, they talk about how on-chip VDD-VSS rail-collapse
should be limited to only 25-30 mV due to DC drop.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

I performed my own analysis a few weeks ago on a rather large
design (~15 Watts at 2.5V). I charted how much VDD-VSS collapse
vs amount of decoupling capacitance, and I found that the
amount of benefit rolled off at about 8X. Meaning, after you've
added decoupling capacitance roughly 8X that of the total
load capacitance, the benefit of additional capacitance was
minimal.

Also, for our design (not to be taken as a generic statement),
we looked at four sources for capacitance:

        * power grid self capacitance
        * N-well capacitance
        * static-gate capacitance
        * intentionally added discrete capacitance

The first two were minimal (< 0.1X of load), the third
provided about 1X of load, and the fourth was our primary
source of capacitance at about 7X of load. For our
design, our analysis showed we needed to add about
20 nF of discrete capacitance.

Enjoy,
Pat

 
>
> Does anyone have some approximate numbers for
> the amount of on-chip capacitance that has been explicitly
> added to large commercial or non-commercial chips?
>
> I'm looking for data as it relates to explicit on-chip
> capacitance to reduce core noise.
>
> As an example, I heard at one point that the DEC Alpha chips
> in the mid 90's used on the order of 50nF of explicit
> capacitance for its core logic.
>
> If there is data on the order of magnitude
> amount of capacitance used on Sun, MIPs, Intel, Motorola, IBM
> uPs, or other large VLSI chips, I would greatly appreciate
> hearing about it.
>
> Thanks
> Dave Chengson Juniper Networks www.juniper.net
> chengson@juniper.net W: (408)745-8189 FAX 408 745-8905
>
>

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