[SI-LIST] : Power Plane Inductance

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From: Moran, Brian P (brian.p.moran@intel.com)
Date: Wed Jul 12 2000 - 14:19:45 PDT


Hi All,

I am trying to do some back of the envelope power delivery analysis, and I
need a number for inductance from a BGA package pad pin escape, to a
decoupling capacitor, located 0.5' to 1.0" from the via site. Can anyone
throw out a good guess, or quote existing data, for power and ground path
inductance from BGA pad to decoupling capacitor pad, for a typical 4 layer
62 mil thick PCB, using 1 oz power planes, with a 50 mil pitch BGA, using
interstitial pin escapes with a 15 mil wide trace, and 25/40 thermals, with
4-8mil spokes. I'm not asking someone to field solve for me, I was just
hoping someone had used similiar geometries in the past, or had some good
rules of thumb they might share. I have data for various configurations of
capacitor pad/via configurations, but nothing for the rest of the path.

Brian Moran
Signal Integrity Engineer
Intel Corporation
Folsom, CA

-----Original Message-----
From: Paul Galloway [mailto:paulg@chip2chip.com]
Sent: Friday, June 30, 2000 6:52 PM
To: si-list@silab.eng.sun.com
Cc: Paul Galloway
Subject: [SI-LIST] : job openings

Chip2Chip, Inc. is an exiting start up with offices in San Jose,
Lowell (MA), and Chapel Hill (NC). We've just received our second
round of funding and are really starting to move, we have some
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Chip2Chip, Inc. has several openings for applications and design
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experience. Descriptions for other openings are also listed on our
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Prefer knowledge of SONET/SDH specification, and experience designing
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Resumes and questions to: paulg@chip2chip.com

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