Date: Tue Jun 20 2000 - 12:03:45 PDT
I sent this E-mail a couple of days ago, but failed to send it to the SI
List. Here 'tis.
Personally, I disagree (albeit, a qualified disagreement) with the first two
Sean Murray wrote:
> I don't know if this has been asked before, but what are the general
> feelings on the use of guard traces to shield clock lines? Is it worth
> it, or the required amount of gnd vias prevents this from being a viable
Because of the phrase "...to shield...," I have interpreted the original
inquiry as dealing with expected radiated emissions and/or cross-coupling
The use of grounded guard traces has many caveats. First, for any "hot"
traces (and clocks certainly qualify here) I recommend stripline only. If
one HAS to use surface traces, then he/she is probably dealing with a
low-cost design that dictates the use of same. The expressed concern for the
multiple vias also implies a dense layout.
Given my interpretations, Doug's "They're unnecessary" comment may very well
apply IF the clock traces are an emission problem, BUT can be routed well
inboard of the printed circuit board (PCB) edges. For such routing, the
clock line emitted fields would have plenty of termination places on the PCB;
hence, radiation would be reduced. Whether the reduced level is acceptable
is another question. However, if cross-coupling is also a major concern,
adding physical separation from other traces is also a necessity; therefore,
the density problem may again come to bear.
My experience has indicated that the use of guard traces introduces some
compensating effects that offset the space concerns while achieving superior
crosstalk and radiated emissions reductions. Specifically, for a four-layer
FR-4 PCB and single-ended clock signals with desired center-to-center (CTC)
signal trace spacing approximately twice the dielectric thickness from trace
to image plane, the addition of guard traces allowed the SAME CTC spacing
while reducing crosstalk by 12 to 14 dB and reducing near-field radiated
emissions (~1/2-inch above the trace) by 6 to 8 dB across the full spectrum
of the clock signal content. The adjacent guard traces add capacitance to
the signal trace, forcing a narrower trace to be used. Sharing of guard
traces between two different signals achieves further space economy, allowing
the CTC spacing to be maintained. The implementation limitations turn out to
be manufacturing limitations (i.e., how small a via hole and associated pad
is available from your PCB manufacturer).
If you doubt this, I have a demonstration PCB that I designed and used to
illustrate these effects in worldwide seminars for Hewlett-Packard (using
their test equipment, of course).
Additionally, Sean, if clock line surface traces are necessary, I also
recommend series source termination and added ground fills on the surface
layers as space and routing permits. Although I assumed the use of
single-ended clock lines in the above commentary, the use of a properly
implemented differential clock source (if compatible with your other
components) could achieve the same results without guard traces.
Michael L. Conn
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