From: Kim Flint ([email protected])
Date: Thu Jun 15 2000 - 20:16:09 PDT
Please excuse this commercial interlude....
ATI has a position open for a Signal Integrity Engineer at our Santa Clara,
CA R&D center. We focus on SOC based products for the PC and consumer
electronic markets at this division, and have some exciting things in the
works. I've been doing some of the SI work here, and find it a fascinating
challenge to mix the demands of high-performance IC's with low-cost,
high-volume system design. If you think this might interest you, please feel
free to contact me (privately!) at [email protected] or 408-572-6383. (Or you
can try Bill Clark at [email protected] or 408-845-6318.)
I'm also looking for more system/board engineers for my group. Since I know
there are a lot of board design types on this list too, I've attached a job
description for that as well.
If you are tired of that boring networking startup, our stuff is way more
Here is our job description:
Signal Integrity Engineer
Be responsible for signal integrity analysis, simulation, and design for
high performance systems based on complex SOC devices. Work closely with
VLSI, Package, and Board designers to ensure high quality signal integrity
for our systems and chips.
- Board and package level transmission line analysis, pre and post route
- IC package 2d/3d modeling and simulation, pinout and padout analysis
- SSO, Ground Bounce analysis
- Specification of I/O buffer requirements
- IBIS model generation and verification
- Power system analysis for planes, decoupling, package substrate,
regulator performance, power/ground pin count
- Provide delay data for timing calculations
- EMI analysis
- Lab characterization of IC and system designs
MSEE or BSEE with equivalent industry experience. Minimum 6 years experience
in high-performance signal integrity engineering. Thorough understanding of
high-speed board, package, and I/O buffer design. Extensive experience with
2d/3d field solvers and transmission line simulators, such as Ansoft,
Pacific Numerics, XTK, and Spice. Experience with Lab techniques for
Familiarity with design needs of PC devices and low-cost consumer products.
PhD or strong mathematics background a plus.
Senior System Design Engineer
Senior system design engineer for ATI's system-on-chip division, developing
cutting edge internet appliance, PC, and multimedia products. This position
will be responsible for specification, design, development, and debug of
state-of-the-art board level systems using ATI's latest SOC products. Board
designs will include desktop PC motherboards, notebook motherboards,
portable consumer electronics products, multimedia systems, and more. Design
debug boards used by the VLSI organization to verify next generation
silicon, and contribute system engineering expertise to specification and
design of the latest system-on-chip products. Successful candidate will be
in a dynamic engineering environment, with the opportunity to participate in
a wide variety of exciting and challenging projects.
- System Hardware Design for next generation PC platforms
- Design of debug motherboards for new SOC ASICs.
- High speed board design
- Schematic generation, guidance of PCB projects through layout and
- System debug and verification
- Definition and verification of signals and pinouts for new IC
- Creation of system specifications
- 4+ years of system and board design experience
- Experience with high speed board design techniques
- Experience with PC architecture and different PC bus protocols
PCI, AGP, USB, Intel/Amd host bus
- Experience with schematic entry, usage of common board design
OrCAD, PADs, etc.
- Experience working with PCB layout designers, PCB fabrication and
- Board level bringup, debug, and verification experience
- Deep system knowledge of one or more of the following areas:
- Desktop PC motherboards
- low-power consumer products
- multimedia systems, audio, video, graphics, etc.
- wireless and networking systems
- Proven ability to deliver complex projects from specification
- Good communication skills
- Experience in Board level pre layout and post layout simulations
for signal integrity analysis.
- background in high-volume, low cost applications
- Understanding of VLSI design process and bringup
Kim Flint 408-572-6383
Manager, System Engineering [email protected]
ATI Research, Inc. http://www.ati.com
**** To unsubscribe from si-list or si-list-digest: send e-mail to
[email protected] In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Wed Nov 22 2000 - 10:50:39 PST