From: Larry Smith ([email protected])
Date: Thu Jun 15 2000 - 09:15:06 PDT
Jan - thanks for your comments. At the frequencies that we are
concerned with, I believe skin effect dominates the losses. If we were
to change the conductivity of the planes, we would change the skin
depth and the frequency where the onset of skin effect occurs.
I decreased the conductivity of the planes in our simulator from 5.8e7
to 5.8e6 (1/10 the conductivity) and saw some reduction in the plane
resonances. But a major reduction in conductivity was required to see
The conductivity on our planes is already too small. We are increasing
the thickness of our copper planes (0.5 oz going to 1 oz and 2 oz) just
to handle the DC current. I would not want to decrease the
conductivity of our power planes at all for high power applications (10's
Best regards, and good luck on the thesis,
> Date: Thu, 15 Jun 2000 10:58:43 +0200
> From: [email protected] (Jan Vercammen)
> To: [email protected]
> Subject: [SI-LIST] : reaction on Larry Smith's thin dielectrics
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> I have followed the discussion on dielectric losses and interplane capacitance with
> In my thesis for obtaining a Msc on Electromagnetic Compatibility I have addressed
> the issue of increasing the lossess in the PCB power plane by studying the plate
> separation and the copper plate conductivity. These issues are more complicated
> and they were but a small part of the my work.
> Nevertheless I found that there could be a potential benifit by manipulating the plate
> conductivity as Larry states in his first email.
> I have included two pdf files. The first pdf file displays the simulation AND measurement
> results on a test vehicle. The details are in the thesis. The power plane measures
> about 22cm times 28cm and has an interplane separation of 160micron. The substrate is
> standard FR4. I excite the plane with a triangular pulse that injects about 200mA of
> current into the plates. The measurement is at a nearby location with a wideband
> osciloscoop using a 50R measuremnt setup. The plane also contains a shortcircuit.
> The simulator used is based on Spice, it uses frequency dependent models to incorporate
> skin and dielectric substrate losses (details in thesis).
> The first pdf file p86_1.pdf displays the measured result curve 'p86_1' and the simulated
> result curve 'vp86_1'. We used the text book value for the conductivity of copper.
> The simulation compares favorable with the simulation. The simulation hints at the
> fact that the plate conductivity of copper foil is likely larger than that of
> pure copper. It is alos possible that other effects, such as the foil surface, could
> have an effect.
> The second pdf file p86_badcond.pdf displays a simulation with again the text book value
> for the conductivity (curve vp86_1) and another simulation with a 100 time
> worse conductivity and all other parameters the same (curve 'vp86_1_badcond).
> The simulation shows that the lower conductivity removes the higher frequency content,
> without actually increasing the voltage drop. Of course this is but one specific
> situation. One should be careful drawing general conclusions. Maybe the lower
> conductivity plate system will have DC voltage drop problems.
> There are still some questions to be answered. The text book value for the conductivity
> of copper is not necessarily the correct value for copper foil used in PCBs and it
> is very likely somehwat larger. The conductivity of the foil could
> be controlled by adding controlled contaminations. Specialist in shielding know that
> miniute contaminations can have a dramatic influence on the conductivity and maybe
> the copper foil plating process could be manipulated to get controlled conductivity.
> I am not in the position to take the initiative for such investigations, but I can
> imagine that other R&D groups are better situated to address these problems. Is there
> anyone who could undertake such an investigation?
> My thesis is public. Currently I am waiting for its final evaluation and because other
> people also have requested copies I can not imagine that this would interfere with
> with the examination process. Therefor you are welcome to retrieve it from my
> company's website at:
> Unzip the file and untar into directory thesis were you will find a README
> and a postscript file final_root0.ps. You can view it with ghostview or send it to
> a postscript printer (144 pages).
> Jan Vercammen
> EMC engineering Agfa-Gevaert NV, Belgium
> [email protected]
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