**From:** Howard Johnson (*[email protected]*)

**Date:** Tue Jun 13 2000 - 15:34:26 PDT

**Next message:**Weber Chuang: "[SI-LIST] : ferrite bead"**Previous message:**Larry Smith: "Re: [SI-LIST] : pcb plane cap and mixed bypass cap value...."**Maybe in reply to:**Barry Ma: "[SI-LIST] : Upper limit of interplane capacitance"**Next in thread:**Chan, Michael : "RE: [SI-LIST] : Upper limit of interplane capacitance"

I advocate thin dielectric layers, using ordinary FR-4

dielectric materials. I don't like using high-dielectric

materials for power-and-ground plane separation.

As we go to higher frequencies, in order to attain ever-lower values

of spreading inductance, we will need thinner and thinner power-ground

spacing. If we cannot make our power-ground

dielectric layers sufficiently thin, we may have to switch to

a layer-cake approach with several pairs of power-ground layers.

To deal with our resonance problems, I'm hoping that someone

will develop some materials with somewhat higher loss

properties that FR-4 and copper. Either a more lossy dielectric,

or perhaps a copper layer with a surface treatment that

increases its skin-effect loss (like plating with tin or

something less conductive that copper) could begin to help

in this area.

By the way, if you want to model power-plane effects yourself

using one-dimensional transmission-line modeling tools (like Spice),

there is a cute way to model a radial transmission line that some

of you may find interesting. I picked up this trick from

a previous email on the si-list:

From: "Mike Degerstrom" <[email protected]>

Date: Mon, 17 May 1999 14:20:52 -0500

Subject: Decoupling caps and power plane effects

I've added some elaboration...

Assume first that we are looking at a *round* PCB, and injecting

current between the power and ground planes exactly in the

center. At the point of injection there is a finite annular ring

of current injected by the signal via. Call the radius of this

ring R. From that point, the current spreads out radially away from

the via.

Now let K be some small number just a little bigger that unity.

Divide the board into a set of concentric rings, starting with

the first ring of size R, the next of size R*K, the next of size

R*K*K, and so on, in a geometric progression of radii.

For K sufficiently close to unity, (perhaps 1.01), a signal

propagating radially through any particular ring will

experience, over the short radial extent of the ring, a fairly

constant diameter.

Therefore, each concentric ring behaves like a very wide

transmission line (for ring n the effective width equals the

circumference, or 2*pi*R*(K^^n)), and constant height H, and

fixed length (R*K^^n - R*K^^(n-1)) = R*(K^^(n-1))*(K-1).

Given a particular value of H and W,

Z(r,h) = 120*pi*(H/W)*(1/sqrt(Er))

Figure the impedance of each transmission structure,

and call it Z(n).

What we have now is a succession of transmission lines,

of various increasing lengths, and various decreasing

impedances Z(n). That is a structure which can be modeled

(given a sufficiently large number of keystrokes) in Spice.

How many sections do you need? I don't know. If it was

me doing the modeling, I'd use an automated mathematical

processing tool like MathCad to generate and couple together

the segments.

This one-dimensional modeling approach can do some neat

tricks. For one, it directly shows the relation between impedance

and time. That is, over very short periods of time, the

input impedance of the structure is fairly high (that

forms the basis for claims that planes don't work at

high frequencies). Over longer periods of time the impedance

is less. You can see this effect directly in the step

respond using SPICE.

Also, if you simulate enough time to show the wavefront going

to the end of the structure and then bouncing back, you can

see resonance phenomena.

If you terminate the end of the structure (as if you had added

a circumferential termination all the way around the edge of

the card) the resonances go away.

You can place a capacitor in the structure to simulate the effect

of a ring of capacitors some finite distance away from the

injection point.

What you can't do with a one-dimensional model is investigate

the effect of 2-D placement of bypass capacitors.

Best regards,

Dr. Howard Johnson

*>Return-Path: <[email protected]>
*

*>Delivered-To: [email protected]
*

*>X-Sender: [email protected]
*

*>Date: Tue, 13 Jun 2000 12:17:25 -0700
*

*>To: [email protected]
*

*>From: Larry Smith <[email protected]> (by way of Howard Johnson
*

<[email protected]>)

*>Subject: RE: [SI-LIST] : Upper limit of interplane capacitance
*

*>
*

*>Larry - thanks for your comments.
*

*>
*

*>Discrete decoupling capacitors run out of gas at about 500 MHz. We
*

*>have managed to reduce the mounting inductance for 0603 size capacitors
*

*>to 300 pH. If we assume 200 pH for the internal capacitance of the
*

*>capacitors, we have a total of 500 pH which is 942 mOhms at 500 MHz.
*

*>Discrete capacitors are not doing much good.
*

*>
*

*>You can use the series resonant frequency and low ESR capacitors to
*

*>drive towards a low impedance at 500 MHz. But using the formula f0 =
*

*>1/(2pi*sqrt(LC)), the capacitance required to hit 500 MHz with 500 pH
*

*>ESL is about 200 pF. We get 225 pF for every square inch of power
*

*>planes (4 mil dielectric, FR4), so unless we are going to use more than
*

*>one discrete capacitor every square inch, they will not be of much use.
*

*>
*

*>A far better solution is to get the low impedance from the power
*

*>planes. Using FR4 BC technology from Hadco (2 mils) we get 450 pF per
*

*>square inch. Dupont, 3M and other materials vendors are beginning to
*

*>advertise 1 mil dielectric cores that are compatible with PCB
*

*>manufacture. That brings us up to 900 pF per square inch. We are
*

*>beginning to get away from straight FR4 technology, but this is where
*

*>our industry needs to go if low impedance power distribution is
*

*>required at high frequency. If this thin dielectric has some high K
*

*>material in it, so much the better.
*

*>
*

*>But almost more importantly, the thin dielectric material has low
*

*>spreading inductance. High capacitance and low inductance results in
*

*>lower impedance power planes and that is very good. There is no point
*

*>in putting a bunch of low impedance decoupling capacitors on a PCB if
*

*>you don't have low impedance power planes to hook them up.
*

*>
*

*>The skin effect losses (alpha of a transmission line) go as
*

*>Rskin/2*Z0. Istvan Novak (Sun) has demonstrated how low impedance
*

*>power planes naturally damp out the cavity resonances because of skin
*

*>effect losses as the dielectric thickness drops to a fraction of a mil.
*

*>At more than 1 GHz, dielectric loss also contributes to the damping.
*

*>In this case, loss is a good thing.
*

*>
*

*>So, the solution to low impedance power distribution above several
*

*>hundred MHz lies in thin dielectric power plane technology. This is
*

*>much more effective than discrete decoupling capacitors. (But Discretes
*

*>are not going to go away because they will be required at frequencies
*

*>below several hundred MHz.) With the attenuation from thin dielectric
*

*>power planes, the size of the planes (6x6 inches) becomes of minor
*

*>importance. I would not advocate carving up power planes, that only
*

*>leads to other problems.
*

*>
*

*>regards,
*

*>Larry Smith
*

*>Sun Microsystems
*

*>
*

*>> From: "Larry Miller" <[email protected]>
*

*>> Subject: RE: [SI-LIST] : Upper limit of interplane capacitance
*

*>> Date: Mon, 12 Jun 2000 11:08:29 -0700
*

*>>
*

*>> An excellent treatment.
*

*>>
*

*>> Taking all of this into account, what would you say is a rough limit
*

*>> frequency for PCBs and coupling caps as a circuit packaging methodology? It
*

*>> seems like it would be size dependent. For a 6 inch square effective board,
*

*>> maybe 1 GHz? Do you think you can extend this up by putting in stitched
*

*>> moats to subdivide a board into smaller effective sheets? Hoo-ha?
*

*>>
*

*>> Larry Miller
*

*>>
*

*>> > -----Original Message-----
*

*>> > From: Larry Smith [SMTP:[email protected]]
*

*>> > Sent: Monday, June 12, 2000 10:45 AM
*

*>> > To: [email protected]; [email protected]
*

*>> > Cc: [email protected]
*

*>> > Subject: Re: [SI-LIST] : Upper limit of interplane capacitance
*

*>> >
*

*>> > We have experimental data on power plane resonances and good model to
*

*>> > hardware correlation. There has been a lot of discussion of these
*

*>> > topics on si-list recently and I feel that it is time to comment.
*

*>> > Everyone in the industry is using power planes for power distribution,
*

*>> > but there does not seem to be good agreement for the behavior of these
*

*>> > planes or how to model and measure them.
*

*>> >
*

*>> > Take for example a pair of 1 oz copper planes separated by 4 mils of
*

*>> > FR4 with dimensions of 6 inches on a side. The planes behave like a
*

*>> > parallel plate capacitance at low frequency. The capacitance is
*

*>> > epsilon*area/thickness and works out to be 225 pF/square_inch or 8.1 nF
*

*>> > for the plane pair.
*

*>> >
*

*>> > The time of flight down the length of the planes is 1 nSec for e0=4
*

*>> > (FR4). A full wave will stand in the cavity at 1 GHz and a half wave
*

*>> > at 500 MHz and create high impedance resonances. From a point source,
*

*>> > the planes behave like a radial transmission line, but in my view, this
*

*>> > not very important. If a point anywhere on the board (except dead
*

*>> > center) begins to stimulate the planes at a multiple of 500 MHz (half
*

*>> > wavelength), energy builds up in the resonant cavity. After several
*

*>> > cycles, there are plane waves bouncing back and forth between the open
*

*>> > circuit ends of the planes. High voltage is always found at the edges
*

*>> > and high current nodes are found in the center of the planes. It doesn't
*

*>> > matter where the source is because the resonance is a function of the
*

*>> > cavity dimensions. All that is important is that the cavity got
*

*>> > stimulated.
*

*>> >
*

*>> > These effects can be measured nicely with a network analyzer. Connect
*

*>> > port 1 and port 2 just about anywhere on the board. It is best to
*

*>> > leave at least an inch between them so that the vertical connections do
*

*>> > not couple with each other. Fifty Ohm transmission line soldered to
*

*>> > empty decoupling capacitor pads work nicely for this. At low
*

*>> > frequency, the network analyzer will show you an impedance that
*

*>> > decreases with frequency at 20 dB per decade. If you do the math on
*

*>> > the impedance you calculate the plane capacitance, Z=1/(j*omega*C). At
*

*>> > frequencies below cavity resonance, all points on the power planes are
*

*>> > at the same potential at any given point in time and it does not matter
*

*>> > where the probes are located. For the 6x6 square inch example, this is
*

*>> > true up to about 100 MHz (1/4 wavelength stands in the board at 250
*

*>> > MHz).
*

*>> >
*

*>> > There are many ways to model this, but my favorite is a matrix of
*

*>> > transmission lines. We divide the board into an 8x8 array of 64
*

*>> > sections. Transmission lines are used to connect the nodes in an x-y
*

*>> > fashion. The transmission line parameters are easily calculated from
*

*>> > plane capacitance, inductance and resistance. Ray Anderson mentioned
*

*>> > some of these calculations last week. The calculations have been
*

*>> > documented by the HP guys at EPEP conferences and Journal articles over
*

*>> > the past couple of years. HSpice will allow .ac analysis on frequency
*

*>> > dependent resistors which are used for skin and dielectric loss.
*

*>> > HSpice also enables parameter calculations and it is possible to
*

*>> > calculate dB = 20*Log(V/I) to simulate the impedance that matches the
*

*>> > output of the Network analyzer.
*

*>> >
*

*>> > We have very good model to hardware correlation on bare fabs (unstuffed
*

*>> > PCB's) that correctly shows the capacitance at low frequencies and all
*

*>> > important cavity resonances up to several GHz. For cavity resonances,
*

*>> > the position of the probes on the power planes is very important to get
*

*>> > the low impedance dips associated with 1/4 lambda to a board edge. The
*

*>> > high impedance peaks occur at the same frequency everywhere on the
*

*>> > board but the magnitude of the peak varies with position. The height
*

*>> > of the peaks and depth of the valleys are determined by the Q of the
*

*>> > circuit which is a strong function of skin and dielectric loss at
*

*>> > cavity resonant frequencies.
*

*>> >
*

*>> > But all that changes as soon as decoupling capacitors and components
*

*>> > are mounted on the power planes. With well chosen decoupling
*

*>> > components, it is possible to make the impedance vs frequency flat up
*

*>> > to 100 MHz. The capacitors force he impedance of the planes to -60 or
*

*>> > -70dB from 30 kHz to 100 MHz where the bare fab was much higher than
*

*>> > that, perhaps -30 dB with a slope associated with 8.1 nF. Decoupling
*

*>> > capacitors still dominate the cavity resonances between 100 and 400
*

*>> > MHz, but the position on the power planes now becomes important.
*

*>> > Decoupling capacitor placement is important at these frequencies.
*

*>> >
*

*>> > One very important impedance peak occurs between the decoupling
*

*>> > capacitors (that have gone inductive) and the relatively pure
*

*>> > capacitance of the power planes. These two elements form a parallel LC
*

*>> > tank circuit with a high impedance resonance, usually at several
*

*>> > hundred MHz. If the discrete capacitors are well distributed on the
*

*>> > power planes (as they usually are on our products), we have an
*

*>> > inductance and capacitance per square area and position on the PCB is
*

*>> > not important. This impedance peak must be carefully managed,
*

*>> > particularly if we have taken advantage of low ESR capacitors to
*

*>> > minimize the number of mounted components. It is usually more of
*

*>> > an EMI problem than an SI problem.
*

*>> >
*

*>> > We notice several dB of change above 100 MHz when a large uP is
*

*>> > inserted or removed from it's socket. It takes a lot of careful
*

*>> > modeling of the active devices and the decoupling capacitors mounted on
*

*>> > pads and vias to get the simulated models to match the hardware
*

*>> > measurements. (but that is beyond the scope of this already long
*

*>> > email..).
*

*>> >
*

*>> > regards,
*

*>> > Larry Smith
*

*>> > Sun Microsystems
*

*>> >
*

*>> > > Date: Fri, 09 Jun 2000 14:44:30 -0700
*

*>> > > From: "Douglas C. Smith" <[email protected]>
*

*>> > >
*

*>> > > I am not a guru on this topic either, however I have thought
*

*>> > > that there is more than a radial transmission line here, in
*

*>> > > that the two dimensional transmission line has lots of funny
*

*>> > > mid-plane loads in the form of bypass capacitors that give
*

*>> > > reflectons (I am talking of power to ground plane here).
*

*>> > > That combined with the open sides would make for a driving
*

*>> > > point impedance that would should be quite lumpy with
*

*>> > > frequency. I am ignoring the lossy loads of the devices
*

*>> > > themselves which are another set of complicating factors.
*

*>> > >
*

*>> > > Does anyone have experimental data they have taken on this
*

*>> > > handy?
*

*>> > >
*

*>> > > Doug (Smith)
*

*>> > >
*

*>> > > Doug McKean wrote:
*

*>> > > >
*

*>> > > > "Chan, Michael" wrote:
*

*>> > > > >
*

*>> > > > > I would like to point out that what would be the impedance look
*

like

*>> > when
*

*>> > > > > you looks at it from the center of the two plates viewing from the
*

*>> > top? Can
*

*>> > > > > you still qualify it as a rectangular wave guide as the wave is
*

*>> > spread out
*

*>> > > > > in
*

*>> > > > > 360 degree other than in one particular direction. Instead of
*

*>> > calling it the
*

*>> > > > >
*

*>> > > > > traditional "characteristic impedance" I would prefer to see it
*

as "

*>> > driving
*

*>> > > > >
*

*>> > > > > point impedance". Any comment from any guru ????
*

*>> > > >
*

*>> > > > The "equations" come out the same. Just as if you
*

*>> > > > were asking if there would be any difference with
*

*>> > > > the characteristic impedance of a one dimensional
*

*>> > > > transmission line at the end or in the center.
*

*>> > > > Reality would dictate something different with the
*

*>> > > > geometries and cutouts in the planes.
*

*>> > > >
*

*>> > > > But there's a couple of different issues going on
*

*>> > > > with parallel plates structures and quite different
*

*>> > > > in many ways. One structure is that the parallel
*

*>> > > > plates make a transmission line, the other is that
*

*>> > > > they make a waveguide. The transmission line supports
*

*>> > > > electric and magnetic fields in the dielectric as
*

*>> > > > currents move in the plates. The waveguide simply
*

*>> > > > *guides* fields between them. either along the axis
*

*>> > > > of the plates or by reflecting them off the walls.
*

*>> > > >
*

*>> > > > In the case of the plates constituting a transmission
*

*>> > > > line, circulating currents say in the power plane would
*

*>> > > > terminate at the edges. Since there's no termination
*

*>> > > > at the edge, this would cause theoretically a complete
*

*>> > > > positive reflection.
*

*>> > > >
*

*>> > > > Like ripples on a pond, these would create nodes at
*

*>> > > > various points about the planes depending upon many
*

*>> > > > factors geometry being one. Which is in fact the case.
*

*>> > > > Termination of such could not be accomplished with
*

*>> > > > a single point connection such as a resistor.
*

*>> > > >
*

*>> > > > This phenomena cannot be explained when considering
*

*>> > > > the planes as a *waveguide*.
*

*>> > > >
*

*>> > > > - Doug McKean
*

*>> > > >
*

*>> > > > **** To unsubscribe from si-list or si-list-digest: send e-mail to
*

*>> > > > [email protected] In the BODY of message put: UNSUBSCRIBE
*

*>> > > > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
*

*>> > > > si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*>> > > > ****
*

*>> > >
*

*>> > > --
*

*>> > > -----------------------------------------------------------
*

*>> > > ___ _ Doug Smith
*

*>> > > \ / ) P.O. Box 1457
*

*>> > > ========= Los Gatos, CA 95031-1457
*

*>> > > _ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
*

*>> > > / /\ \ ] / /\ \ Mobile: 408-858-4528
*

*>> > > | q-----( ) | o | Email: [email protected]
*

*>> > > \ _ / ] \ _ / Website: http://www.dsmith.org
*

*>> > > -----------------------------------------------------------
*

*>> > >
*

*>> > > **** To unsubscribe from si-list or si-list-digest: send e-mail to
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*>> > > [email protected] In the BODY of message put: UNSUBSCRIBE
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*>> > > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
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*>> > > si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*>> > > ****
*

*>> > >
*

*>> >
*

*>> >
*

*>> > **** To unsubscribe from si-list or si-list-digest: send e-mail to
*

*>> > [email protected] In the BODY of message put: UNSUBSCRIBE
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*>> > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
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*>> > si-list archives are accessible at http://www.qsl.net/wb6tpu
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*>> > ****
*

*>> >
*

*>
*

*>
*

*>**** To unsubscribe from si-list or si-list-digest: send e-mail to
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*>si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
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**Next message:**Weber Chuang: "[SI-LIST] : ferrite bead"**Previous message:**Larry Smith: "Re: [SI-LIST] : pcb plane cap and mixed bypass cap value...."**Maybe in reply to:**Barry Ma: "[SI-LIST] : Upper limit of interplane capacitance"**Next in thread:**Chan, Michael : "RE: [SI-LIST] : Upper limit of interplane capacitance"

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