**From:** Larry Smith (*[email protected]*)

**Date:** Mon Jun 12 2000 - 10:44:57 PDT

**Next message:**Doug McKean: "Re: [SI-LIST] : Current handling capability of etch......"**Previous message:**Coleman, Dave: "RE: [SI-LIST] : Current handling capability of etch......"**Maybe in reply to:**Barry Ma: "[SI-LIST] : Upper limit of interplane capacitance"**Next in thread:**Larry Miller: "RE: [SI-LIST] : Upper limit of interplane capacitance"

We have experimental data on power plane resonances and good model to

hardware correlation. There has been a lot of discussion of these

topics on si-list recently and I feel that it is time to comment.

Everyone in the industry is using power planes for power distribution,

but there does not seem to be good agreement for the behavior of these

planes or how to model and measure them.

Take for example a pair of 1 oz copper planes separated by 4 mils of

FR4 with dimensions of 6 inches on a side. The planes behave like a

parallel plate capacitance at low frequency. The capacitance is

epsilon*area/thickness and works out to be 225 pF/square_inch or 8.1 nF

for the plane pair.

The time of flight down the length of the planes is 1 nSec for e0=4

(FR4). A full wave will stand in the cavity at 1 GHz and a half wave

at 500 MHz and create high impedance resonances. From a point source,

the planes behave like a radial transmission line, but in my view, this

not very important. If a point anywhere on the board (except dead

center) begins to stimulate the planes at a multiple of 500 MHz (half

wavelength), energy builds up in the resonant cavity. After several

cycles, there are plane waves bouncing back and forth between the open

circuit ends of the planes. High voltage is always found at the edges

and high current nodes are found in the center of the planes. It doesn't

matter where the source is because the resonance is a function of the

cavity dimensions. All that is important is that the cavity got

stimulated.

These effects can be measured nicely with a network analyzer. Connect

port 1 and port 2 just about anywhere on the board. It is best to

leave at least an inch between them so that the vertical connections do

not couple with each other. Fifty Ohm transmission line soldered to

empty decoupling capacitor pads work nicely for this. At low

frequency, the network analyzer will show you an impedance that

decreases with frequency at 20 dB per decade. If you do the math on

the impedance you calculate the plane capacitance, Z=1/(j*omega*C). At

frequencies below cavity resonance, all points on the power planes are

at the same potential at any given point in time and it does not matter

where the probes are located. For the 6x6 square inch example, this is

true up to about 100 MHz (1/4 wavelength stands in the board at 250

MHz).

There are many ways to model this, but my favorite is a matrix of

transmission lines. We divide the board into an 8x8 array of 64

sections. Transmission lines are used to connect the nodes in an x-y

fashion. The transmission line parameters are easily calculated from

plane capacitance, inductance and resistance. Ray Anderson mentioned

some of these calculations last week. The calculations have been

documented by the HP guys at EPEP conferences and Journal articles over

the past couple of years. HSpice will allow .ac analysis on frequency

dependent resistors which are used for skin and dielectric loss.

HSpice also enables parameter calculations and it is possible to

calculate dB = 20*Log(V/I) to simulate the impedance that matches the

output of the Network analyzer.

We have very good model to hardware correlation on bare fabs (unstuffed

PCB's) that correctly shows the capacitance at low frequencies and all

important cavity resonances up to several GHz. For cavity resonances,

the position of the probes on the power planes is very important to get

the low impedance dips associated with 1/4 lambda to a board edge. The

high impedance peaks occur at the same frequency everywhere on the

board but the magnitude of the peak varies with position. The height

of the peaks and depth of the valleys are determined by the Q of the

circuit which is a strong function of skin and dielectric loss at

cavity resonant frequencies.

But all that changes as soon as decoupling capacitors and components

are mounted on the power planes. With well chosen decoupling

components, it is possible to make the impedance vs frequency flat up

to 100 MHz. The capacitors force he impedance of the planes to -60 or

-70dB from 30 kHz to 100 MHz where the bare fab was much higher than

that, perhaps -30 dB with a slope associated with 8.1 nF. Decoupling

capacitors still dominate the cavity resonances between 100 and 400

MHz, but the position on the power planes now becomes important.

Decoupling capacitor placement is important at these frequencies.

One very important impedance peak occurs between the decoupling

capacitors (that have gone inductive) and the relatively pure

capacitance of the power planes. These two elements form a parallel LC

tank circuit with a high impedance resonance, usually at several

hundred MHz. If the discrete capacitors are well distributed on the

power planes (as they usually are on our products), we have an

inductance and capacitance per square area and position on the PCB is

not important. This impedance peak must be carefully managed,

particularly if we have taken advantage of low ESR capacitors to

minimize the number of mounted components. It is usually more of

an EMI problem than an SI problem.

We notice several dB of change above 100 MHz when a large uP is

inserted or removed from it's socket. It takes a lot of careful

modeling of the active devices and the decoupling capacitors mounted on

pads and vias to get the simulated models to match the hardware

measurements. (but that is beyond the scope of this already long

email..).

regards,

Larry Smith

Sun Microsystems

*> Date: Fri, 09 Jun 2000 14:44:30 -0700
*

*> From: "Douglas C. Smith" <[email protected]>
*

*>
*

*> I am not a guru on this topic either, however I have thought
*

*> that there is more than a radial transmission line here, in
*

*> that the two dimensional transmission line has lots of funny
*

*> mid-plane loads in the form of bypass capacitors that give
*

*> reflectons (I am talking of power to ground plane here).
*

*> That combined with the open sides would make for a driving
*

*> point impedance that would should be quite lumpy with
*

*> frequency. I am ignoring the lossy loads of the devices
*

*> themselves which are another set of complicating factors.
*

*>
*

*> Does anyone have experimental data they have taken on this
*

*> handy?
*

*>
*

*> Doug (Smith)
*

*>
*

*> Doug McKean wrote:
*

*> >
*

*> > "Chan, Michael" wrote:
*

*> > >
*

*> > > I would like to point out that what would be the impedance look like when
*

*> > > you looks at it from the center of the two plates viewing from the top? Can
*

*> > > you still qualify it as a rectangular wave guide as the wave is spread out
*

*> > > in
*

*> > > 360 degree other than in one particular direction. Instead of calling it the
*

*> > >
*

*> > > traditional "characteristic impedance" I would prefer to see it as " driving
*

*> > >
*

*> > > point impedance". Any comment from any guru ????
*

*> >
*

*> > The "equations" come out the same. Just as if you
*

*> > were asking if there would be any difference with
*

*> > the characteristic impedance of a one dimensional
*

*> > transmission line at the end or in the center.
*

*> > Reality would dictate something different with the
*

*> > geometries and cutouts in the planes.
*

*> >
*

*> > But there's a couple of different issues going on
*

*> > with parallel plates structures and quite different
*

*> > in many ways. One structure is that the parallel
*

*> > plates make a transmission line, the other is that
*

*> > they make a waveguide. The transmission line supports
*

*> > electric and magnetic fields in the dielectric as
*

*> > currents move in the plates. The waveguide simply
*

*> > *guides* fields between them. either along the axis
*

*> > of the plates or by reflecting them off the walls.
*

*> >
*

*> > In the case of the plates constituting a transmission
*

*> > line, circulating currents say in the power plane would
*

*> > terminate at the edges. Since there's no termination
*

*> > at the edge, this would cause theoretically a complete
*

*> > positive reflection.
*

*> >
*

*> > Like ripples on a pond, these would create nodes at
*

*> > various points about the planes depending upon many
*

*> > factors geometry being one. Which is in fact the case.
*

*> > Termination of such could not be accomplished with
*

*> > a single point connection such as a resistor.
*

*> >
*

*> > This phenomena cannot be explained when considering
*

*> > the planes as a *waveguide*.
*

*> >
*

*> > - Doug McKean
*

*> >
*

*> > **** To unsubscribe from si-list or si-list-digest: send e-mail to
*

*> > [email protected] In the BODY of message put: UNSUBSCRIBE
*

*> > si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
*

*> > si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*> > ****
*

*>
*

*> --
*

*> -----------------------------------------------------------
*

*> ___ _ Doug Smith
*

*> \ / ) P.O. Box 1457
*

*> ========= Los Gatos, CA 95031-1457
*

*> _ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
*

*> / /\ \ ] / /\ \ Mobile: 408-858-4528
*

*> | q-----( ) | o | Email: [email protected]
*

*> \ _ / ] \ _ / Website: http://www.dsmith.org
*

*> -----------------------------------------------------------
*

*>
*

*> **** To unsubscribe from si-list or si-list-digest: send e-mail to
*

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*> ****
*

*>
*

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****

**Next message:**Doug McKean: "Re: [SI-LIST] : Current handling capability of etch......"**Previous message:**Coleman, Dave: "RE: [SI-LIST] : Current handling capability of etch......"**Maybe in reply to:**Barry Ma: "[SI-LIST] : Upper limit of interplane capacitance"**Next in thread:**Larry Miller: "RE: [SI-LIST] : Upper limit of interplane capacitance"

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