RE: [SI-LIST] : Bypassing of large fpga's

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From: Barry Ma ([email protected])
Date: Tue Jun 06 2000 - 09:38:07 PDT

Hi Michael and Jim,

I agree with what you both said. The plane cap and the decaps are complementary in whole frequency range. Plane cap takes care of high end, and decaps cover low portion. Then locations of decaps are not critical. And then decaps can be shared by other chips, according to the excellent research conducted by EMC lab at UMR.

There might be a couple of issues we can discus further. What is the frequency boundary for plan cap and decaps? How far can we locate decaps from the IC? How many decaps can be reduced? I’d be very interested in hearing of any input.

I think all depend on the particular frequency spectrum we should take care of. You mentioned “100's of MHz”. I even saw setting 100 MHz as the boundary. It does not mean decaps cannot work at, say, 500 MHz. Just because plane cap could work better.

Barry Ma
[email protected]
On Tue, 06 June 2000, "Greim, Michael" wrote:

 Hi Jim,
I think that you can answer your own question on a number of fronts. At a high level, the answer it depends. If the impedance target of your PDS is satisfied with a decoupling scheme that features only bulk and plane caps you are done. You are correct that their plane caps really only have an effect above a certain freq. However, more impor- tantly, they have a finite amount of capacitance as defined by:
         Cplane = 0.225 * Er * A/d
 by taking a look at your instantaneous current requirements defined by our old favorite:
         Itran = C * dV/dT
 You can determine whether the plane cap can service this need. With a big fine pitch BGA, with lots of simultaneous switching outputs, you will probably need some help. Remember, with the smaller voltage rails, 5% ripple is a pretty small number. I don't believe that any high performance PDS system can be designed with simple rules of thumb, unless it is so over designed that routing resources are heavily clogged and other problems arise.
 Your mileage may vary.
 Best Regards,
 Michael Greim
  -----Original Message-----
  From: Peterson, James F (FL51) [SMTP:[email protected]]
  Sent: Tuesday, June 06, 2000 9:51 AM
  To: [email protected]
  Subject: RE: [SI-LIST] : Bypassing of large fpga's
You mention the ordinary plane cap (stackup configuration which puts pwr and gnd planes close to each other). An excellent tip, but it isn't an effective decoupler at frequencies lower than 100's of MHz. We still need a good mix of "ordinary" caps, right?
  Best regards,
  -----Original Message-----
  From: Barry Ma [mailto:[email protected]]
  Sent: Friday, June 02, 2000 6:45 PM
  To: [email protected]; [email protected]
  Cc: [email protected]
  Subject: Re: [SI-LIST] : Bypassing of large fpga's
  Thanks Mitch.
We don't know what is the highest frequency your project has to treat. If you guys "Thought about buried capacitance", it seems that you wanted to use interplane capacitance to deal with that frequency. They’re two techniques for plane cap:
  (1) Standard Laminates. The plane spacing can be controlled to 4 - 10 mils.
  (2) Buried Capacitance (BC). The spacing can reach to 2 mils.
If you are not ready for BC, you may consider the stackup of adjacent pwr/gnd planes to apply ordinary plane cap.
No matter what plane-cap technique you apply, the number of bypass caps can be reduced, and you don't have to be anxious about the precious real estate on your PCB.
  My 2 cents.
  Barry Ma
  [email protected]
  On Fri, 02 June 2000, [email protected] wrote:
I'll second what Barry said, and add, most any bypassing scheme lends itself to using buried capacitive layers. If you were to just add the capacitive layers to your existing "power" planes, which may or may not be in close proximity to the "ground" planes, you'd enjoy the added capacitance value and probably some decrease in noise.
   References will be provided if required.


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