RE: [SI-LIST] : Board Stackup - again ...

About this list Date view Thread view Subject view Author view

From: Moran, Brian P (brian.p.moran@intel.com)
Date: Tue Jun 06 2000 - 08:27:22 PDT


Doug,

As usual I also agree with Lee. If you can get away without locking
yourself into a particular vendors patented product its always a good idea.
I just used BC because Zycon was alreadya preferred vendor. The 3 mil
pre-preg is a more cost effective solution.

Brian P. Moran

Intel Corporation
Platform Design Engineering
brian.p.moran@intel.com
(916) 356-1912

-----Original Message-----
From: Ritchey Lee [mailto:leeritchey@earthlink.net]
Sent: Monday, June 05, 2000 4:30 PM
To: Moran, Brian P
Cc: 'Doug McKean'; SI - List Discussion Group
Subject: Re: [SI-LIST] : Board Stackup - again ...

Like Brian, I add layers for the express purpose of increasing the
capacitance between planes. However, I don't use BC. Instead, I look at
where I can add two new planes next to two planes already in the stackup.
If
you do this right, you can separate the planes with 3 mils of prepreg and
get
almost twice the capacitance you would otherwise get. In addition, it is
not
necessary to use a patented material such as BC.

Lee

Moran, Brian P wrote:

> Doug,
>
> Most high layer count designs I have done use dual stripline pairs between
> power and ground layers. Its nice if you happen to get power and ground
> adjacent but its hard to guarantee, es[ecially when you have multiple
> voltages. One option I have used is to have a standard 12 layer with no
> adjacent planes and then build a version using BC (buried capacitance)
> pwr/gnd pairs in place of the normal pwr plane positions. This makes it a
> 14 layer stack but the BC spacing is only 2 mils so you get good high
> frequency decoupling without blowing out the stack dimensions.
>
> Brian P. Moran
>
> Intel Corporation
> Platform Design Engineering
> brian.p.moran@intel.com
> (916) 356-1912
>
> -----Original Message-----
> From: Doug McKean [mailto:dmckean@corp.auspex.com]
> Sent: Friday, June 02, 2000 11:25 AM
> To: SI - List Discussion Group
> Subject: [SI-LIST] : Board Stackup - again ...
>
> What are the opinions of separating power and
> ground planes with a signal layer?
>
> Is it a *hard fast rule* that never shall they be separated?
> Are there some caveats conditions that allow separation?
>
> Assuming that everything except stackup remains the same,
> is there some significant measurable difference with say
> a digital board handling clocks around 40 MHz to 80 MHz
> and bus speeds of say PCI, and fsb of 133 (maybe even 200)
> and/or Ethernet with power and ground planes separated with
> a signal layer as opposed to one that has them adjacent?
>
> I've been of the opinion that power and ground planes should
> NEVER be separated, but lately, I'm not so sure about that.
>
> Comments?
>
> - Doug McKean
>
> **** To unsubscribe from si-list or si-list-digest: send e-mail to
> majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
> si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
> ****
>
> **** To unsubscribe from si-list or si-list-digest: send e-mail to
> majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
> si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at http://www.qsl.net/wb6tpu
> ****

**** To unsubscribe from si-list or si-list-digest: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Wed Nov 22 2000 - 10:50:32 PST