RE: [SI-LIST] : Bypassing of large fpga's

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From: Greim, Michael (mgreim@mc.com)
Date: Tue Jun 06 2000 - 07:35:00 PDT


Hi Jim,

I think that you can answer your own question on a number
of fronts. At a high level, the answer it depends. If the
impedance target of your PDS is satisfied with a decoupling
scheme that features only bulk and plane caps you are
done. You are correct that there plane caps really only
have an effect above a certain freq. However, more impor-
tantly, they have a finite amount of capacitance as defined
by:

                Cplane = 0.225 * Er * A/d

by taking a look at your instantaneous current requirements
defined by our old favorite:

                Itran = C * dV/dT

You can determine whether the plane cap can service this
need. With a big fine pitch BGA, with lots of simultanous
switching outputs, you will probably need some help. remember,
with the smaller voltage rails, 5% ripple is a pretty small number.
I don't believe that any high performance PDS system can be
designed with simple rules of thumb, unless it is so over designed
that routing resources are heavily clogged and other problems
arise.

Your mileage may vary.

Best Regards,

Michael Greim

> -----Original Message-----
> From: Peterson, James F (FL51) [SMTP:james.f.peterson@honeywell.com]
> Sent: Tuesday, June 06, 2000 9:51 AM
> To: si-list@silab.eng.sun.com
> Subject: RE: [SI-LIST] : Bypassing of large fpga's
>
> Barry,
>
> You mention the ordinary plane cap (stackup configuration which puts pwr
> and
> gnd planes close to each other). An excellent tip, but it isn't an
> effective
> decoupler at frequencies lower than 100's of MHz. We still need a good mix
> of "ordinary" caps, right?
>
> best regards,
> Jim
>
> -----Original Message-----
> From: Barry Ma [mailto:barry_ma@altavista.com]
> Sent: Friday, June 02, 2000 6:45 PM
> To: mcgiffb@ttc.com; cadpro2k@dacafe.com
> Cc: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Bypassing of large fpga's
>
>
> Thanks Mitch.
>
> Bill,
>
> We don't know what is the highest frequency your project has to treat. If
> you guys "Thought about buried capacitance", it seems that you wanted to
> use
> interplane capacitance to deal with that frequency. There two techniques
> for
> plane cap:
>
> (1) Standard Laminates. The plane spacing can be controlled to 4 - 10
> mils.
> (2) Buried Capacitance (BC). The spacing can reach to 2 mils.
>
> If you are not ready for BC, you may consider the stackup of adjacent
> pwr/gnd planes to apply ordinary plane cap.
>
> No matter what plane-cap technique you apply, the number of bypass caps
> can
> be reduced, and you don't have to be anxious about the precious real
> estate
> on your PCB.
>
> My 2 cents.
>
> Regards,
> Barry Ma
> bma@ANRITSU.com
>
> -----------
> On Fri, 02 June 2000, cadpro2k@dacafe.com wrote:
>
> >
> > Bill,
> >
> > I'll second what Barry said, and add, most any bypassing scheme lends
> > itself to using buried capacitive layers. If you were to just add the
> > capacitive layers to your existing "power" planes, which may or may not
> > be in close proximity to the "ground" planes, you'd enjoy the added
> > capacitance value and probably some decrease in noise.
> >
> > References will be provided if required.
> >
> > Mitch
> >
> > ---------Included Message----------
> > > Date: 2 Jun 2000 10:22:40 -0700
> > > From: "Barry Ma" <barry_ma@altavista.com>
> > > Reply-To: "Barry Ma" <barry_ma@altavista.com>
> > > To: <mcgiffb@ttc.com>
> > > Cc: <si-list@silab.eng.sun.com>
> > > Subject: [SI-LIST] : Re: [SI-LIST] Bypassing of large fpga's
> > >
> > > Bill,
> > >
> > > I cannot understand what you said: "Thought about buried
> capacitance, but our
> > > power plane scheme doesn't lend itself to that." ... I don't
> think
> it's a good
> > > idea to separate the pwr and gnd planes. ...
> > >
> > > Regards,
> > > Barry Ma
> > > bma@ANRITSU.com
>
>
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